This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.

Rambus offers a flexible work environment, embracinga hybrid approach fora mosta office-baseda roles.aaEmployeesaare encourageda toa spend an average of at leasta three days per weeka onsite,a allowing fora twoa daysa of remote work.aa

• Contribute to the architecture and micro-architecture of next generation PCIea IPa

• Implement these designs in System Veriloga

• Collaborate with the verification team to verify the IPsa

• Participate in prototyping of the IPs in cutting edge FPGAsa

• Contribute to support of existing generations of the IPsa

Required:

• RTL coding: Verilog / System Verilog
• Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
• 8+ years of experience with RTL Design
• Good English skills, communication skills, and willingness to work with an international team.a

Additional Desirable skills:

• Knowledge of PCIe / CXL

Rambus offers a competitive compensation packageaincludingabase salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

TheUSsalary range for thisfull-timeposition is $108,300to $201,100.Our salary ranges aredeterminedby role,leveland location. The successful candidates starting pay will bedeterminedbased on job-related skills, experience, qualifications, worklocationand market conditions.

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