Location: Burlington, Ottawa, ON or Bristol, UK (Hybrid – 4 days in office Mon- Thurs)
Job Summary
We are looking for a Principal NPI Product Engineer to take ownership of new product development programs — from early-stage silicon development through full production transfer. Working closely with cross-functional teams across design, validation, test, characterization, quality, and operations, you will be a key technical contributor and program driver for our high-performance optical and analog/mixed-signal IC portfolio in cutting-edge CMOS and BiCMOS technologies.
Key Responsibilities
1. NPI Program Ownership & Cross-Functional Collaboration 25%
- Drive NPI programs from product concept through final release, ensuring product conformance to specifications and seamless transfer to full-volume manufacturing
- Lead and coordinate with cross-functional teams including Design, Marketing, Validation, Test Engineering, Characterization, Quality & Reliability, Applications Engineering, and Operations
- Own backend NPI development tracking through product transfer; lead milestone reviews of program logistics, timelines, and deliverables
- Prepare and own NPI product release deliverables and OSAT-related manufacturing documentation, ensuring accuracy and completeness
2. Design for Testability & Manufacturability 35%
- Define and drive Design for Testability (DfT) and Design for Manufacturability (DfM) requirements for NPI products
- Lead development, implementation, verification, and optimization of ATE test programs in collaboration with test engineering
- Drive product characterization, correlation, and release activities to ensure adherence to product specifications and quality standards
- Own finalization of datasheet specifications and ATE production test limits through data-driven, statistically validated limit-setting processes
3. Characterization, Data Analysis & Yield Optimization 30%
- Develop and own product characterization plans for wafer-level and bench tests across product specifications and operating conditions
- Lead data analysis of ATE and bench characterization results across PVT variations, including ATE-to-bench correlation studies and process capability analysis
- Drive yield modeling activities and lead DOE planning and execution to support yield analysis, test time reduction, and test optimization
- Lead product validation and reliability qualification activities in collaboration with Test, Characterization, Validation, and Reliability Engineering teams
- Identify yield loss Pareto opportunities and drive targeted solutions to closure
4. Manufacturing Quality, Failure Analysis & Continuous Improvement 10%
- Monitor yields and quality metrics across processing steps; proactively identify and act on trends and anomalies
- Review and own test coverage, test limits, and guard-band decisions
- Lead failure analysis and root cause investigations for field returns and RMA cases; drive CAPA development and closure
- Partner with foundry process and packaging engineering teams to resolve issues during wafer fabrication, packaging, die sort, and final package test
- Identify and implement product lifecycle cost reduction and continuous improvement opportunities
Qualifications
- BS in Electrical Engineering or a related field (MS strongly preferred)
- 10+ years of experience in semiconductor product engineering, test engineering, or design engineering
- Proven ownership of silicon bring-up, characterization, and production transfer programs
- Hands-on experience with ATE test development, ATE-to-bench correlation, and production test limit setting
- Strong foundation in DfT and DfM principles
- Proficiency with statistical analysis tools such as JMP or Excel; scripting/automation in Python, TCL, or equivalent
- Excellent analytical, problem-solving, and cross-functional communication skills
- Background in analog/mixed-signal or optical IC characterization (TIA, CDR, LimitAmp, high-speed SerDes)
- Familiarity with high-speed ATE platforms such as Advantest or Teradyne
- Experience with JEDEC reliability qualification methodologies (HTOL, HAST, ESD, latch-up)
- Exposure to ATPG, MBIST, or boundary scan DFT flows
- Experience engaging directly with foundry and OSAT partners
Why Join Semtech
- Work on cutting-edge CMOS and BiCMOS ICs powering next-generation 400G / 800G / 1.6T optical networking infrastructure
- Full program ownership from Day 1 — you drive products, not just support them
- Global, collaborative team with sites in Burlington ON, Bristol UK, Aguascalientes MX, San Diego CA, and an Asia Hub
- Technically rigorous culture with strong cross-functional exposure and direct access to design, reliability, and fab teams
- Competitive compensation, benefits, and professional development opportunities
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
