Job Details:Job Description:Come build what's next in scalable, high-performance silicon.
At Intel, our standard cell libraries sit at the foundation of every product we build. This role is more than designing circuits; it's about shaping how we deliver power, performance, and scalability across future nodes and products.
We're looking for a Principal Engineer who thrives on solving hard problems, someone who can bring deep circuit expertise and help define the direction of library architecture, DTCO, and design methodology. Your work will directly influence how our designs scale across CPU, GPU, and emerging architectures.
Why this role matters
As process nodes become more complex, delivering competitive Power, Performance and Area (PPA) and Vmin requires more than incremental improvements. This role plays a key part in defining the next generation of library design, balancing usability, scalability, and performance while enabling product teams to move faster with confidence.
A day in this role
In this role, you will:
- Shape standard cell library strategy, including content definition, cell selection, and ecosystem usability.
- Drive circuit innovation for high-performance and low-voltage operation, especially in sequential and clocking circuits.
- Lead PPA and Vmin optimization efforts, working through complex tradeoffs across performance, power, and area.
- Drive optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs
- Directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners
- Partner with DTCO, product design teams, and EDA partners to align on scalable solutions.
- Guide and mentor circuit designers, helping raise the bar on design quality and methodology.
- Lead or contribute to working groups, bringing clarity and convergence across diverse stakeholders.
- Develop and refine circuit methodology, including naming conventions, modeling approaches, validation frameworks, and best practices.
- Analyze silicon and design data to identify outliers, debug issues, and drive improvements.
- Partner with process technology teams to define and refine process requirements for standard cell development.
- Help define forward-looking directions, including new circuit topologies and design approaches.
- Mentor and develop technical leaders within the organization, fostering a culture of growth, collaboration, and excellence
Big challenges you'll take on.
- Balancing aggressive PPA and Vmin targets in highly complex and low-voltage regimes.
- Simplifying and scaling the library ecosystem across multiple nodes and product lines.
- Driving technical alignment across teams with different priorities and constraints.
- Making high-impact technical decisions where data may be incomplete or evolving.
- Translating complex circuit and system challenges into practical, scalable solutions.
Qualifications
- In-depth understanding of MOSFET electrical characteristics, transistor device level physics, layout and variability at advanced technology nodes
- Working knowledge of transistor level design of static circuits including state retaining elements such as latches and flops in circuit design, standard cell development, or related domains.
- Understanding of std cell circuit design tradeoffs across power, performance, area and Vmin
- Experience with standard cell characterization tools and Spice circuit simulations
- Experience in identification, design and verification of cells targeted to improve product level PPA
- Ability to lead analyze data, identify trend and effectively communicate conclusion
- Expertise in low-power, high-performance circuit techniques, including clocking and sequential elements.
- Solid understanding of PPA tradeoffs, Vmin behavior, and variation impacts.
- Ability and willingness to proactively support development of junior engineers
- Collaborative mindset and great team player
- Excellent oral and written communication skills
- Strong problem-solving skills in ambiguous, complex environments.
Qualifications:Minimum Qualifications
- Ph.D. or Master's degree
- With 10+ years of industry experience with foundation IP design, design-technology co-optimization & advanced semiconductor technology.
Preferred Qualifications
- Good track record of technical leadership and delivery
- Experience in designing around local layout effect & technical leadership and/or management
- Some understanding or experience of block-level design tool for feedback to optimize standard cell library content and/or design
- Background in compact modeling, characterization, or EDA tool interaction.
- Experience working across CPU, GPU, or SoC design teams.
- Publications, patents, or recognized technical contributions.
- Experience leading working groups or driving cross-org technical alignment.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
