Principal Engineer-Design

Job Description:

We’re looking for a highly motivated, creative Principal Digital Design Engineer to join our engineering team and lead development of digital IP and SoC-level integration for mixed-signal microcontrollers. This is a hands-on role spanning RTL design, integration, and signoff verification—with broad cross-functional exposure to analog, architecture, validation/test, and product teams.

Key Responsibilities:

• Own and drive digital block and subsystem design from concept through tape-out, partnering with architects and system engineers on definition and requirements

• Develop high-quality RTL (Verilog / System Verilog) for digital peripherals and IP (8/32-bit class blocks), emphasizing robust, reusable design

• Lead block- and SoC-level verification and integration, including:

  • Digital verification (simulation/regressions, assertions/coverage)

  • UPF / low-power intent integration and verification

  • AMS / mixed-signal verification collaboration with analog teams

  • Static Timing Analysis (STA) support and closure coordination

  • Power and IR analysis and support with implementation/signoff teams

  • Physical Design / APR (Place & Route) collaboration and signoff support, including synthesis handoff, floorplanning awareness, timing/DRC/LVS closure coordination, and ECO support with PD teams

• Provide technical leadership via design reviews, documentation, debug leadership, and project planning

• Collaborate closely with analog design, architecture, product and test engineering, applications, and marketing to ensure silicon and product success

Requirements/Qualifications:

Qualifications/Requirements

• B.S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification

• Strong foundations in digital logic / finite state machine design, computer architecture, RTL coding, and SoC integration techniques

• Working knowledge of Physical Design / APR concepts and flows (synthesis, floorplanning, place-and-route, CTS, ECO), and ability to partner effectively with PD teams on timing/power/DFM closure

• Familiarity with industry EDA flows / tools (Cadence, Synopsys, Siemens), Linux, Windows

• Scripting skills (Python / Perl / Tcl) for productivity and flow automation

• Excellent debug, analytical thinking, and clear communication skills; comfortable driving alignment across teams

• Thrives in a team-oriented, fast-paced environment with a strong ownership mindset and continuous learning attitude

Preferred qualification:

• M.S. in Electrical Engineering, Computer Engineering, or related field

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking

Physical Requirements:

80% sitting, 10% walking, 10% standing

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

The annual base salary range for this position, which could be performed in the US, is $75,000- $232,000.*