ADI is seeking a Principal EDA Engineer with deep expertise in Calibre-based physical verification, code development, and tapeout support for advanced analog and mixed-signal programs. This role serves as a technical authority for signoff methodology, rule deck implementation, verification flow development, and critical tapeout readiness across multiple projects and process nodes. The engineer in this role will lead the development and optimization of Calibre-driven flows, build code and tools that extend verification capability, and partner closely with design and layout teams to resolve high-impact issues from project setup through final signoff. Key Responsibilities • Calibre Technical Authority: Serve as a recognized expert for Calibre-based physical verification flows, including DRC, LVS, ERC, PERC, parasitic extraction, and signoff methodology • Verification Flow Development: Define, develop, maintain, and optimize Calibre verification flows and supporting infrastructure for analog and mixed-signal design teams • Rule Deck and Code Development: Write, debug, and enhance SVRF and TVF rule sets, along with custom code and scripts that extend Calibre capabilities, improve debug efficiency, and strengthen flow reliability • Tapeout Support Leadership: Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification closure items • Foundry Rule Integration: Drive intake, validation, integration, and versioning of foundry rule files and process updates for advanced-node programs • Critical Debug and Escalation: Resolve the most complex verification, runset, extraction, and rule deck issues affecting project execution or tapeout schedules • Project Enablement: Support new project setup, verification environment readiness, and early issue identification so design teams can avoid downstream signoff risk • Tooling and Automation: Build internal tools, scripts, dashboards, and reporting utilities that improve verification visibility, XOR analysis, runtime efficiency, and license or compute usage • Technical Guidance and Mentorship: Provide training, documentation, and expert guidance to engineers using verification flows and signoff methodologies across the organization Must Have Skills • Calibre Expertise: Expert-level proficiency with Mentor Calibre across DRC, LVS, ERC, PERC, extraction, and signoff flows • Rule Deck Development: Deep hands-on experience writing, debugging, and maintaining SVRF and TVF rule sets for advanced-node verification • Code and Tool Development: Strong experience developing code, scripts, and internal tools that utilize and extend Calibre workflows, including automation, result parsing, analysis, and debug support • Tapeout and Signoff Support: Proven experience supporting tapeouts, final verification closure, waiver flows, antenna-related issues, and foundry-facing signoff requirements • Advanced Node Experience: Strong experience with TSMC design rules, rule deck integration, and physical verification challenges at nodes such as 16nm, 5nm, and 4nm • Debug Leadership: Ability to lead resolution of complex backend verification and extraction issues with significant project or schedule impact • EDA Environment Knowledge: Strong understanding of Linux-based EDA environments, compute infrastructure, license usage, and version-controlled design data workflows • Cross-Functional Technical Support: Ability to work effectively with analog layout, design, CAD, and project teams in a fast-paced multi-project environment • Analog Physical Design Understanding: Strong understanding of analog layout practices, physical verification issues, and signoff expectations Preferred Education and Experience • BS or MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent combination of education and 10+ years of related experience • Experience supporting digital physical design or place-and-route verification flows • Experience with Perforce for design data management • Experience with Cadence Virtuoso customization, including SKILL, bindkeys, or layout environment setup • Experience building GUI-based tools, reporting systems, or verification analytics dashboards • Experience with EDA license management, compute optimization, or multi-site verification infrastructure • Familiarity with AI-assisted methods that improve verification productivity, debug efficiency, or flow effectiveness We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply. #LI-PG1 Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $159,638 to $239,457. • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.