5-7 years of hands-on experience in physical design for advanced node tapeouts
Strong understanding of PPA (Power, Performance, Area) limiters from RTL
Proven ability to coordinate with microarchitects to optimize RTL
Experience managing both in-house and outsourced physical design flows
Familiarity with multi-die and multi-chiplet designs is a plus
Knowledge of reticle-max design processes is advantageous
Experience with high power density and AI chip designs is beneficial
Responsibilities
Manage and execute the physical design process for A-0 and A-1 systems
Decide on in-house versus outsourced design tasks
Oversee the integration of outsourced processes with in-house efforts
Collaborate with microarchitects to address PPA limiters
Ensure design flows meet project specifications and timelines
Benefits
Opportunity to work on cutting-edge technology in advanced node designs
Collaborative environment with a focus on innovation
Exposure to both in-house and outsourced design processes
Potential for professional growth in a rapidly evolving field
Engagement with multi-die and AI chip design projects
Full Job Description
What We're Looking For:
We're looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort.
Ideal Candidates:
Ideal candidates will have:
Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts
Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them
Experience both with in-house and outsourced physical design flows
Nice to Have:
Experience with physical design process for multi-die/multi-chiplet/MCM designs
Experience with physical design process for reticle-max or near reticle max designs
Experience with very high power density chips
Experience with the physical design process for AI chips
Experience with the physical design process of analog and mixed signal blocks and macros
