Physical Design Engineer

Qualifications

• 5-7 years of experience in physical design engineering
• Proficiency with TSMC 2NP/3NP technology nodes
• Strong understanding of end-to-end physical design flow
• Experience with low-power design techniques (MultiVt, Multivoltage)
• Familiarity with physical verification tools and methodologies
• Ability to collaborate effectively with cross-functional teams
• Experience in advanced nodes (7nm, 5nm, 3nm or below)

Responsibilities

• Perform end-to-end physical design flow including floorplanning and power planning
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC, and signoff violations
• Implement low-power design techniques such as power gating and clock gating
• Conduct physical verification and signoff using STA and SI analysis
• Collaborate with RTL, microarchitecture, DFT, and CAD teams
• Drive methodology improvements and automation through scripting

Benefits

• Competitive pay
• Healthcare insurance options (Dental, Medical, Vision)
• Major holidays off
• Paid sick leave as per state law