Title: Physical Design Engineer Location: Palo Alto, CA (Full Onsite) JD for PD: - Exposure to TSMC 2NP/3NP is must
- Perform end-to-end physical design flow:
- Floor planning
- Power planning (PG grid, IR)
- Placement & optimization
- CTS (Clock Tree Synthesis)
- Routing
- Post-route optimization
- chieve timing closure across all modes and corners
- Resolve DRC, LVS, ERC and signoff violations
- Handle low-power design techniques:
- Multi-Vt, Multi-voltage (UPF)
- Power gating, clock gating
- Perform physical verification and signoff:
- STA (Primetime)
- SI / Crosstalk
- IR drop & EM analysis
- Work on advanced nodes (7nm, 5nm, 3nm or below)
- Collaborate with:
- RTL & Micro-architecture teams
- DFT & Test engineers
- Foundry and CAD teams
- Debug complex timing, congestion, power, and variability issues
- Drive methodology improvements and automation (scripts/flows)
Benefits: Danta offers a compensation package to all W2 employees that are competitive in the industry. It consists of competitive pay, the option to elect healthcare insurance (Dental, Medical, Vision), Major holidays and Paid sick leave as per state law.
The rate/ Salary range is dependent on numerous factors including Qualification, Experience and Location.
#ZR