Master's degree in Electrical Engineering with 5+ years of industry experience or PhD with 3+ years
Strong programming skills in Python and other scripting languages
Experience in developing workflow orchestration tools for hardware development
Familiarity with Kubernetes and containerization
Experience implementing regression frameworks
Proficiency in SQL or other databases like MongoDB
Intimate knowledge of hardware design workflows for Physical Design and RTL/DV
Responsibilities
Drive and develop PD flows and methodologies for advanced technologies from scratch
Help create repeatable and predictable design and process agnostic PD flows
Develop flow infrastructure for efficient design under tight schedules
Collaborate with PD team leads to propose end-to-end build and signoff flows
Build regression frameworks to enhance design efficiency
Create quality checking utilities for high design efficiency
Establish a unified environment for specifying design collaterals and flow dependencies
Coordinate with 3rd party vendor resources for project alignment
Benefits
Comprehensive benefits package
Meaningful equity opportunities
10% annual bonus potential
Flexible compensation based on experience and location
Full Job Description
Efficient is seeking a CAD Lead - PD flows/infrastructure to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc). This role is in a newly formed hardware engineering group and is the seed hire for this discipline. You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future.
This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
Drive and develop PD flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
Help develop repeatable, predictable , design and process agnostic PD flows.
Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.
Work closely with PD team leads to propose and develop end to end build and signoff flows.
Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools.
Develop collateral quality checking utils to ensure high design efficiency.
Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips...) and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration).
Work with 3rd party vendor resources and coordinate their work.
Continuously work on improving flow consistency and efficiency in the context of multiple product lines.
Required Qualifications
Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
Strong python other scripting programming skills.
Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)
Familiarity with kubernetes and containerization
Experience implementing regression frameworks
SQL or other database proficiency (MongoDB ..)
Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
Excellent scripting skills in TCL, shell and python.
Desired Qualifications & Experience Requirements
Experience in full chip RTL/DV and PD flows.
Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
Definition of design constraints for static timing analysis (synthesis, pre/post-cts, sign-off) and corners/voltage definitions.
Experience in integrating analog or mixed-signal macro on top-level design.
Experience in verifying IP collaterals.
We offer a competitive base salary for this role, generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
