PE Logic Design

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you. 

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. 

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces 

• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data 

• Collaborate closely with verification team to shape test plans and improve verification coverage 

• Work with physical design team to understand and resolve timing, power, and congestion challenges 

• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary 

• Provide technical support to FAE team on pre-sales customer engagements 

• Provide technical support to AE team on post-sales customer deliveries 

• Strong System Verilog/Verilog RTL design expertise 

• Questa/Incisive/VCS simulator experience 

• Python/Perl/TCL scripting experience 

• Ability to learn quickly and work independently 

• Solid communication and project management skills 

• 10+ years of logic design experience (ASIC/FPGA) with BSEE, or  

• 8+ years of logic design experience (ASIC/FPGA) with MSEE 

Definite Plus: 

• ASIC synthesis, timing constraint, CDC/RDC experience 

• UVM Verification experience 

• Memory (HBM, LPDDR) expertise 

• AMBA AXI or CHI design experience 

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  

The US salary range for this full-time position is $127,400 to $236,600. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. 

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