Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or related field.
• 1-3 years of industry or relevant academic/internship experience in mixed-signal design verification or IC design.
• Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).
• Understanding of HDL languages (Verilog, SystemVerilog) and introductory knowledge of Verilog-A/AMS.
• Solid grasp of fundamental analog circuits and digital logic basics.
• Basic familiarity with Linux environments and scripting (Python, Bash, or Skill) is a plus.
• Exposure to issue-tracking tools (e.g., GitLab) and requirements management systems (e.g., Jama Connect).

Responsibilities

• Run and debug top-level AMS simulations to verify interactions between analog front-ends and digital logic.
• Assist in writing and maintaining behavioral models and testbenches using Verilog and SystemVerilog.
• Verify power-up/power-down sequences and reset circuitry across voltage and temperature corners.
• Validate register maps and EEPROM configurations against design specifications.
• Log and track verification bugs using GitLab issue tracking to support tapeout readiness.
• Collaborate with Analog, Digital Design, and Systems Engineering teams to review coverage metrics and support testcase closure.

Benefits

• Collaborative global engineering environment.
• Opportunity to work on cutting-edge automotive and industrial integrated circuits.
• Exposure to senior technical leads and mentorship opportunities.