Mid Level ASIC Design Engineer

Tensordyne

$120K — $145K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 3+ years of ASIC design experience, particularly in RTL logic design for multi-million gate ASICs using Verilog or System Verilog.
  • Experience with IP integration, including CPU IP within SoC designs.
  • Knowledge of ARM/RISC-V/MIPS Architectures and associated memory hierarchies.
  • Familiarity with AMBA/APB/AXI protocols and various processor peripheral interfaces.
  • Hands-on experience with front-end ASIC development tools and methodologies, especially in low power design.
  • Motivated self-starter eager to contribute to a fast-paced startup environment.
  • B.S. in Electrical or Computer Engineering; M.S. preferred.

Responsibilities

  • Author microarchitecture specifications and participate in reviews.
  • Implement complex RTL designs for the ASIC.
  • Integrate various CPU and IP components into the subsystem.
  • Collaborate with physical design engineers to optimize implementation and resolve timing issues.
  • Analyze code coverage and provide feedback for closure to the verification team.
  • Conduct diagnostic tests and assist with software bring-up post-silicon.

Benefits

  • Opportunity to work on cutting-edge technology in autonomous driving.
  • Dynamic startup culture fostering innovation and growth.
  • Collaborative work environment with cross-disciplinary teams.
  • Exposure to advanced AI architectures and design challenges.
Full Job Description
About the role:

As a member of Tensordyne's ASIC team, you will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. These ASICs closely couple novel computational accelerator units, compute, interconnects, networking and 3rd-party IP blocks as needed to redefine the next generation of tokenomics for inference.

Your responsibilities will be wide-ranging and span at minimum the following:

Responsibilities:
  • Work with architecture on reconciling changes with respect to micro-architecture
  • Define microarchitecture and document
  • Select and integrate 3rd-party IP blocks
  • Collaborate with design verification engineers
  • Run, analyse frontend synthesis and address all issues
  • Collaborate with backend teams on place-and-route guidance and timing closure
  • Ability to leverage GenAI usage across all workflows, while retaining ownership and quality of all generated collateral

Required Qualifications:
  • 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
  • Experience in IP integration, specifically CPU IP into SoC.
  • Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
  • Familiarity with AMBA/APB/AXI Protocol
  • Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
  • Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
  • Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
  • Previous experience with timing closure at high frequencies is a plus.
  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads
  • Self-starter and highly-motivated to work in a dynamic start-up environment.
  • B.S. (M.S. preferred) degree in Electrical or Computer engineering.


Tensordyne's culture was built on the following values that are equally important to us as business:
  • Put people first. We only succeed when our people succeed.
  • Ethics and integrity always; Being open, honest, and respectful of everyone.
  • Think Big. Be ambitious and have audacious goals.
  • Aim for excellence. Quality and excellence count in everything we do.
  • Own it and get it done. Results matter!
  • Make Each Person Better together than they would be as an individual.
  • Embrace each others' differences.
  • Embrace that there will be differences.

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