Role OverviewWe're looking for an exceptional Senior Mid-End ASIC Engineer to own synthesis, timing convergence, implementation readiness, and logical design quality across our AI accelerator roadmap. This is a deeply technical, hands-on engineering role responsible for transforming high-quality RTL into implementation-ready netlists while driving timing closure strategy, constraint development, physical-aware optimization, and close collaboration between RTL designers and backend implementation partners. You will serve as the technical bridge between architecture, RTL, verification, and physical implementation.
Key ResponsibilitiesSynthesis Methodology & Ownership- Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
- Establish signoff criteria and methodology for synthesis deliverables.
Hands-On Synthesis & Constraint Development- Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
- Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
- Drive continuous improvement of synthesis QoR.
Timing Closure Leadership- Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability.
- Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions.
- Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation.
Physical-Aware Optimization- Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.
- Ensure RTL is implementation-friendly from the outset.
Cross-Functional Execution- Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
Vendor Technical Leadership- Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.
AI-Enabled Engineering- Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
Required Qualifications- 12+ years of ASIC implementation experience, including multiple successful tapeouts.
- Expert-level proficiency in synthesis methodology and flow development.
- Deep expertise in timing closure across complex, multi-million-gate designs.
- Expert-level command of Cadence Genus and/or Synopsys Design Compiler.
- Strong SDC expertise, including constraint development and MMMC environments.
- A solid grasp of RTL design principles and implementation-friendly coding practices.
- Hands-on experience with advanced process nodes at 5nm and below.
- Strong Tcl and Python scripting ability for automation and flow development.
- Excellent debugging and root-cause analysis skills.
Preferred Qualifications- Experience with AI accelerators, CPUs, or GPUs.
- Familiarity with LPDDR, PCIe, or SerDes interfaces.
- Exposure to chiplet-based architectures and multi-clock SoC designs.
Leveling & ScopeWhile this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
What Success Looks LikeWithin one year, this person will have established a production-grade synthesis methodology, delivered predictable timing closure, reduced implementation iterations, produced high-quality implementation-ready RTL, and built a scalable methodology to support future ASIC generations.
Why Join Us?- Play a foundational role in shaping the synthesis and timing closure methodology for next-generation AI inference accelerators.
- Work at the cutting edge of AI hardware, directly influencing chips built to power frontier AI workloads.
Compensation & BenefitsThe base salary range for this role is $190,000 - $280,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
Benefits & PerksWe want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
Health and wellness- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
Time off and flexibility- Unlimited paid time off - we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
Compensation and future- Competitive salary and equity
- 401(k) with company matching, eligible from day one
Visa SupportThis position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
