5+ years of experience in microarchitecture for advanced node tapeouts
Proven track record of owning microarchitecture for key blocks
Strong grasp of PPA (Power, Performance, Area) optimization techniques
Familiarity with system-level architecture and its interaction with microarchitecture
Experience integrating microarchitecture blocks into larger systems
Responsibilities
Collaborate with architects to translate specifications into RTL
Lead the microarchitecture design for A-0 and A-1 systems
Work closely with physical design teams to ensure successful silicon implementation
Analyze and optimize microarchitecture for improved PPA
Integrate microarchitecture blocks into broader system architecture
Benefits
Opportunity to work on cutting-edge technology in advanced nodes
Collaborative environment with experienced architects and engineers
Potential for career growth in a rapidly evolving field
Access to resources for professional development
Engagement in innovative projects, particularly in AI chip design
Full Job Description
What We're Looking For:
We're looking for microarchitects to own key blocks in the A-0 and A-1 systems. You will work alongside the architects to translate specifications into implementable RTL and then work with the PD teams to turn it into silicon.
Ideal Background:
Ideal candidates will have:
Experience owning the microarchitecture of at least one block in multiple advanced node tapeouts
Deep understanding of impact of microarchitecture upon PPA, and levers available to improve PPA
Understanding of system level architecture and the impact of microarchitecture upon system architecture
Understanding of integration of blocks into broader system
Nice to Have:
Experience with microarchitecture of AI chip blocks, especially matrix multiplication engines
Knowledge of matrix multiplication engine numerics and effects upon microarchitecture
Experience with microarchitecture at 5nm and below nodes
Experience with physical design process at 7nm and below nodes
