5-7 years of experience in microarchitecture with a focus on advanced node tapeouts
Proven ability to enhance performance, power, and area (PPA) through microarchitectural decisions
Strong grasp of system-level architecture and its relationship with microarchitecture
Experience integrating microarchitectural blocks into larger systems
Familiarity with AI chip microarchitecture, particularly matrix multiplication engines (preferred)
Knowledge of numerical effects on microarchitecture (preferred)
Experience with physical design processes at 7nm and below (preferred)
Responsibilities
Own key microarchitectural blocks in A-0 and A-1 systems
Collaborate with architects to convert specifications into RTL
Work with physical design teams to transition designs into silicon
Analyze and optimize microarchitecture for improved PPA
Integrate microarchitectural components into broader system architecture
Benefits
Collaborative work environment with leading experts in the field
Opportunity to work on cutting-edge technology in advanced nodes
Engagement in impactful projects that shape future products
Access to professional development and training resources
Potential for career advancement in a rapidly evolving industry
Full Job Description
What We're Looking For:
We're looking for microarchitects to own key blocks in the A-0 and A-1 systems. You will work alongside the architects to translate specifications into implementable RTL and then work with the PD teams to turn it into silicon.
Ideal Background:
Ideal candidates will have:
Experience owning the microarchitecture of at least one block in multiple advanced node tapeouts
Deep understanding of impact of microarchitecture upon PPA, and levers available to improve PPA
Understanding of system level architecture and the impact of microarchitecture upon system architecture
Understanding of integration of blocks into broader system
Nice to Have:
Experience with microarchitecture of AI chip blocks, especially matrix multiplication engines
Knowledge of matrix multiplication engine numerics and effects upon microarchitecture
Experience with microarchitecture at 5nm and below nodes
Experience with physical design process at 7nm and below nodes
