Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Qualcomm Technologies, Inc. is seeking a SoC Limits Management Architect on the HW power team. You will define how our next-generation systems balance high performance against physical, electrical and thermal constraints.
You will bridge hardware IP, system software, and product requirements to design a holistic Limits Management architecture and guide product definition through early life cycle involvement.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- MS or PhD in Electronics or Computer Engineering, or equivalent with focus on computer architecture and power/performance analysis.
- 6+ years of ASIC design, verification, validation, integration, or related work experience (5+ years if Master's; 4+ years if PhD).
- Experience with power management and low-power design methodologies.
- Strong C/C++ development skills for architectural modeling and FW prototyping, alongside Python for data analysis, performance profiling, and workflow automation
Responsibilities
- Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
- Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
- Drive organizational consensus on feature ROI and oversee Post-Silicon Validation to ensure alignment with architectural intent.
- Help with post silicon power correlation to match with pre-silicon power models and simulations with actual physical measurements taken from silicon .
Pay range and Other Compensation & Benefits: $145,600.00 - $218,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
