Role SummaryWe are seeking an IC Package Design Engineer to join our ASIC team. In this role, you will lead the physical layout, modeling, and analysis of advanced semiconductor packaging solutions for high-performance integrated circuits (ICs). You will collaborate closely with cross-functional teams, including IC Design, Signal/Power Integrity (SI/PI), PCB Layout, Mechanical, Thermal, and Test Engineering, as well as substrate vendors and OSAT partners to deliver robust, cost-effective packaging from concept through volume production.
Responsibilities- End-to-End Package Layout: Own physical layout execution, including die placement, bump assignment, floor planning, ball map optimization, bump-to-ball fan-out planning, stack-up definition, and layer planning.
- Advanced Packaging Implementations: Design and develop advanced IC packaging solutions, including flip-chip BGA (FCBGA), System-in-Package (SiP), and 2.5D/3D IC architectures (e.g., interposers, CoWoS, EMIB, FOWLP).
- Silicon, Package & Board Co-Design: Partner closely with silicon and system teams to align on die/package/PCB co-design, floor planning, ball map, and interposer routing.
- High-Speed & Power Delivery Network: define and route high speed interfaces (e.g., DDR, PCIe, SerDes), design robust Power Delivery Networks (PDN) with high di/dt requirement
- EDA Tooling: Create, manage, and validate complex package layouts using industry-standard EDA tools (e.g., Cadence APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition).
- Verification & Signoff: Run Design Rule Checking (DRC), Layout vs. Schematic (LVS) checks, netlist verification, and strict Design for Manufacturing (DFM/DFT) reviews.
- Manufacturing Collateral: Generate and validate complete manufacturing collateral (Gerbers, ODB++, BOMs) for tapeout and manufacturing release.
- Multi-Disciplinary Convergence: Work directly with SI/PI, thermal, and mechanical engineering teams to achieve design convergence across power, signal integrity, thermal, and mechanical reliability constraints.
- Vendor & OSAT Integration: Interface with foundries, substrate vendors, and OSAT partners to evaluate design feasibility, select packaging materials and design rules, maximize manufacturing yield, and execute smooth tapeouts.
- Bring-up & Test Support: Assist in lab bring-up, debugging, and silicon validation for packaged devices; collaborate with test engineering teams on probe card and test socket interface design.
- Workflow Automation: Develop and implement scripting tools (e.g., Python, Tcl, Perl, MATLAB) to automate layout flows and enhance design efficiency.
- AI/ML Innovation: Explore and drive adoption of AI/ML-enabled methodologies (e.g., predictive analytics, layout optimization, automated rule checks) to scale productivity and decision-making.
Qualifications- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or a related field.
- Experience: 3+ years (5+ years preferred) of hands-on experience in semiconductor package and substrate layout design, particularly for high-speed (SerDes) and high di/dt IC applications.
- EDA Tools Proficiency: Proven expertise with industry-standard packaging EDA tools such as Cadence Allegro APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition Package Designer, or Calibre/KLayout.
- Technical Fundamentals: Strong foundational knowledge of electromagnetics, impedance control, crosstalk minimization, substrate materials, thermal management, and mechanical reliability.
- Manufacturing Standards: Solid understanding of DFM/DFT principles, JEDEC standards, DRC/LVS signoff flows, and reliability qualification processes.
- Advanced Packaging Experience: Hands-on experience with heterogeneous integration, chiplet architectures, silicon interposers, and 2.5D/3D IC packaging technologies is preferred.
- Ecosystem & Vendor Track Record: A strong track record of working directly with top-tier OSATs, substrate manufacturers, and foundry packaging teams is preferred.
- Automation & Scripting: Experience writing scripts (Python, Tcl, Perl, MATLAB) for workflow automation or leveraging modern AI/ML applications within engineering workflows is preferred.
Pay DisclosureThe salary range for this role is $171,000 - $272,000 for Irvine, CA based applicants and is $186,000 - $296,000 for Palo Alto, CA based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee's position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards.
We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian's 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.
