Micron Technology

HBM SoC Physical Design Engineer

Micron Technology • $120K — $150K *
Richardson, TX 75080In-Person
Consumer Technology
8 - 10 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of SoC physical design experience, especially for advanced nodes.
  • Proficient in EDA tools such as Cadence and Synopsys.
  • Strong grasp of STA fundamentals, timing closure methods, and clocking principles.
  • Experience with power delivery methods and intent planning.
  • Understanding of physical verification processes like DRC and LVS.

Responsibilities

  • Manage physical design for SoC blocks, handling floor-planning and optimization.
  • Achieve timing closure across various scenarios, coordinating with RTL and architecture teams.
  • Spearhead integration of complex IP ensuring physical integrity and timing accuracy.
  • Conduct physical signoff processes and efficiently tackle violations.
  • Collaborate with DFT teams to meet scan/MBIST requirements without compromising designs.
  • Engage with manufacturing teams to ensure quality and manufacturability of builds.
  • Support tape-out processes and assist in post-silicon debug efforts.

Benefits

  • Choice of medical, dental, and vision plans to suit individual and family needs.
  • Income protection programs for unforeseen illness or injury.
  • Paid family leave for work-life balance.
  • Generous paid time-off and holiday benefits.
Full Job Description
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best-in-class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations.

Key Responsibilities
  • Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
  • Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
  • Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
  • Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
  • Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
  • Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
  • Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
  • Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.


Required Qualifications
  • Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
  • Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
  • Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
  • Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
  • Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.


Preferred Qualifications
  • Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
  • Minimum 10 years of experience in a related field.
  • Proven ability to mentor and develop engineers early in their careers.


As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

About Micron Technology

Micron Technology Careers

Join the vibrant team at Micron Technology, a leader in memory and storage solutions, and propel your career into the future of technology. At Micron, we are committed to fostering a culture of diversity and innovation, offering a range of job opportunities that encourage professional growth and leadership development.

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Learn more about Micron Technology
Size
43,000 employees
Market Cap
$53.7 billion
Industry
Manufacturing & Automotive
Net Income
$2.9 billion
Founded
1978
5 Year Trend
+8.6%
Revenue
$22 billion
NASDAQ
MU
* Ladders Estimates

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