About the RoleAs an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their unique needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop and influence future hardware architectures towards efficient training and inference on our models. If you are excited about efficiently distributing a large language model across devices, dealing with and optimizing system-wide/rack-wide networking bottlenecks and eventually tailoring the compute pipe and memory hierarchy of the hardware platform, simulating workloads at different abstractions and working closely with our partners, this is the perfect opportunity!
This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
Key Responsibilities- Co-design future hardware for programmability and performance with our hardware vendors
- Assist hardware vendors in developing optimal kernels and add support for it in our compiler
- Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory hierarchy features
- Build system performance models at different abstraction levels and carry out analysis to drive decisions on scale up, scale out, front end networking
- Work with machine learning engineers, kernel engineers and compiler developers to understand their vision and needs from high performance accelerators
- Manage communication and coordination with internal and external partners
- Influence the roadmap of hardware partners to optimize them for OpenAI's workloads.
- Evaluate potential partners' accelerators and platforms.
- As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.
Qualifications- 4+ years of industry experience, including experience harnessing compute at scale and optimizing ML platform code to run efficiently on target hardware.
- Strong experience in software/hardware co-design
- Deep understanding of GPU and/or other AI accelerators
- Experience with CUDA, Triton or a related accelerator programming language
- Experience driving Machine Learning accuracy with low precision formats
- Experience with system performance modeling and analysis to optimize ML model deployment
- Strong coding skills in C/C++ and Python
- Are familiar with the fundamentals of deep learning computing and chip architecture/microarchitecture.
- Able to actively collaborate with ML engineers, kernel writers, compiler developers, system engineers, chip architects/microarchitects
Preferred Skills- PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing. Compilers or other Systems
- Strong understanding of LLMs and challenges related to their training and inference
