7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
Strong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
Strong scripting skills in Python, Tcl, or similar languages.
Ability to independently own DFT architecture and drive cross-functional technical decisions.
Responsibilities
Define and own chip-level DFT architecture, including scan insertion and test access infrastructure.
Drive DFT insertion and integration across RTL, synthesis, and physical design.
Own DFT verification, ATPG pattern generation, and fault coverage analysis.
Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns.
Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools.
Define technical requirements and oversee contracted DFT work with external partners.
Benefits
Opportunity to shape DFT infrastructure for innovative computing architectures.
Hands-on technical leadership role with end-to-end ownership of silicon testability.
Collaboration with cross-functional teams and external partners.
Work on unconventional computing systems that push the boundaries of technology.
Full Job Description
The Role
As a Design-for-Test (DFT) Engineer at Normal, you will own the DFT architecture and implementation for our next-generation, physics-inspired ASICs, from early RTL design through tapeout and silicon bring-up. You will define and drive scan/ATPG, memory built-in self-test (MBIST), and boundary-scan strategies, working closely with RTL, verification, physical design, and silicon product engineering teams.
This is a hands-on technical leadership role with end-to-end ownership of silicon testability. You will establish DFT methodologies, guide external implementation partners, and ensure our designs are ready for manufacturing test. You'll work on unconventional computing architectures where testability must be considered from the beginning, with the opportunity to shape the DFT infrastructure for an entirely new class of silicon. What You Will Own
DFT Architecture: Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
Implementation & Integration: Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.
Test Coverage & Signoff: Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.
Manufacturing Test Readiness: Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns and test collateral to our manufacturing partners, and documentation for ATE integration, silicon bring-up, and diagnosis.
Methodology & Tooling: Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools, supporting future ASIC programs.
External Partner Collaboration: Define technical requirements, oversee contracted DFT work, and review deliverables to ensure quality and integration with Normal's silicon development process.
What Makes You a Great Fit
7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
Strong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
Strong scripting skills in Python, Tcl, or similar languages.
Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams.
Bonus Points
Experience establishing DFT architecture and methodology from the ground up for a new ASIC program.
Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.
Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.
Experience working with external DFT implementation partners or managing outsourced DFT deliverables.
Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
Experience using AI-assisted or agentic tools to automate silicon design and verification workflows.
