5-7 years of experience in analog circuit design and development
Proven track record of developing analog IP from specification to GDSII
Experience with memory technologies such as SRAM and DRAM at the core level
Proficient in Cadence tools including Virtuoso and Spectre
Strong understanding of noise and variation effects on silicon performance
Responsibilities
Lead the full analog development cycle from research to exploratory design
Develop or acquire analog IP for integration into Normal Silicon
Direct or assist in the development of analog EDA tools
Evaluate memory designs, focusing on SRAM, DRAM, and CIM architectures
Design and characterize custom bitcells in both schematic and layout
Benefits
Opportunity to work on cutting-edge mixed-signal technology
Collaborative environment with cross-functional teams
Ownership of end-to-end analog development process
Exposure to unique computational architectures
Potential for innovation in throughput-per-watt performance
Full Job Description
The Role
As an Analog Hardware Engineer, you will build the core mixed-signal technology powering our unconventional computing architecture.
You will design unique analog circuits, creating library cells as well as macros, to support a unique computational architecture. Working alongside silicon architecture, digital, and layout teams, you will own the end-to-end analog development from clean-sheet circuit design through parasitic extraction and silicon bring-up to unlock unprecedented throughput-per-watt.
What You Will Own
Analog design flow methodology: lead the full analog development cycle including research, exploratory design
Develop or acquire analog IP for use in Normal Silicon
Acquire or help direct analog EDA tool development
Evaluation of memory designs, including SRAM, DRAM, and CIM architectures
What Makes You a Great Fit
Developed analog IP from spec to GDSII in modern technologies, taped out and brought up.
Worked on memory technologies (i.e. SRAM, DRAM) on core level (bitcell arrays and peripheral circuits)
Designed and characterized custom bitcells in schematic and layout
Fluent in the Cadence flow: Virtuoso, Spectre, Assembler, Extraction, Layout, HSMC, Characterization
Deep understanding of noise and variation and their impacts on silicon performance and reliability
Bonus Points
Lead, taped out, brought up CIM chips
Experienced and comfortable in a chip measurement environment for debug and characterization
Have used AI and/or scripting languages (i.e. Python, Perl) to automate design flows and data post-processing
