As a Hardware Engineer focused on accelerator design, you will contribute to the development of custom AI accelerators and high-performance compute hardware that underpin Meta's data center infrastructure at scale. In this role, you will work across digital design, power delivery, signal integrity, and board-level electrical engineering to bring accelerator systems from concept to production, directly enabling the AI workloads that power Meta's products and services.
Responsibilities
Design and validate electrical systems for custom AI accelerator hardware, including PCB layout review, power delivery network analysis, and signal integrity assessment
• Develop and execute hardware bring-up plans for accelerator boards and system-level platforms in data center environments
• Collaborate with silicon, firmware, and thermal engineering teams to define electrical requirements and resolve cross-domain design constraints
• Perform pre- and post-silicon electrical characterization, including power rail measurements, eye diagram analysis, and high-speed SerDes validation
• Develop and maintain electrical schematics and design documentation for accelerator subsystems
• Support design-for-manufacturability reviews and work with contract manufacturers to resolve electrical yield and reliability issues
• Analyze failure modes and conduct root cause investigations for electrical faults identified during validation or field deployment
• Contribute to the definition of electrical test strategies and automated test equipment setups for accelerator hardware qualification
• Engage with component vendors and suppliers to evaluate and qualify power management ICs, connectors, and high-speed interconnects for accelerator platforms
Minimum Qualifications
• BS in Electrical Engineering, Computer Engineering, or a related technical discipline
• 2+ years of experience in electrical or hardware engineering with a focus on high-performance compute, accelerator, or data center hardware design
• 2+ years of experience with PCB schematic capture, layout review, and signal integrity analysis for high-speed digital interfaces (e.g., PCIe, DDR, HBM, or SerDes-based links)
• 2+ years of experience with power delivery network design and analysis, including decoupling strategy, voltage regulator selection, and power integrity simulation
• Experience with hardware bring-up, electrical characterization, and debugging using lab instrumentation such as oscilloscopes, network analyzers, and power analyzers
Preferred Qualifications
• Experience with custom ASIC or GPU accelerator board design, including co-design with silicon teams on package and board-level electrical interfaces
• Exposure to hardware reliability and qualification standards relevant to data center infrastructure (e.g., JEDEC, IPC)
• Experience using simulation tools such as SPICE, HyperLynx, or Ansys SIwave for signal and power integrity analysis
• Familiarity with thermal-electrical co-design considerations for high-TDP accelerator systems in rack-scale data center deployments
