Bachelor's or Master's in Electrical/Computer Engineering or related field
3+ years in FPGA verification
Responsibilities
Develop and execute comprehensive verification plans
Create and maintain test benches using UVM and SystemVerilog
Write and debug test cases for various design scenarios
Perform code and functional coverage analysis
Identify and resolve issues with design engineers
Document verification results and reports
Participate in design reviews and contribute to strategy
Stay updated on verification methodologies and tools
Full Job Description
Title: FPGA Verification Engineer Location: Santa Clara, CA/On-Site Long Term
Mandatory Areas Must Have Skills - FPGA Verification Engineer Skill 1 - 8 + Years of in FPGA Skill 2 - 5 +Years of Exp in UVM Skill 2 - 5 +Years of Exp in System Verlilog
Good To have Skills Skill 1 - Yrs of Exp -N/A Skill 2 - Yrs of Exp -N/A Skill 3 - Yrs of Exp -N/A Skill 4 - Yrs of Exp -N/A Mandatory if Applicable Domain Experience (If any ) -N/A Must have Certifications -N/A Prior UST experience - Y / N #NAME?
Job Description:
We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.
Key Responsibilities: • Develop and execute comprehensive verification plans for FPGA designs. • Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog). • Write and debug test cases to verify functionality, performance, and corner cases. • Perform code coverage and functional coverage analysis. • Identify and debug issues, working closely with design engineers to resolve them. • Document verification results and provide clear and concise reports. • Participate in design reviews and contribute to the overall verification strategy. • Stay up-to-date with the latest verification methodologies and tools.
Skills Required: • Strong understanding of FPGA design principles and architectures. • Proficiency in SystemVerilog and UVM verification methodology. • Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). • Knowledge of code coverage and functional coverage analysis. • Excellent debugging and problem-solving skills. • Strong communication and collaboration skills.
Requirements • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. • 3+ years of experience in FPGA verification. • Experience with scripting languages (e.g., Python, Perl). • Familiarity with hardware description languages (e.g., VHDL, Verilog).
