FPGA Verification Engineer

Qualifications

• 8+ years of experience in FPGA engineering
• 5+ years of experience in UVM (Universal Verification Methodology)
• 5+ years of experience in System Verilog
• Bachelor's or master's degree in electrical or computer engineering or a related field
• Experience with scripting languages such as Python or Perl
• Familiarity with VHDL or Verilog

Responsibilities

• Understand and apply FPGA design principles
• Utilize System Verilog and UVM for verification
• Employ verification tools like QuestaSim and Synopsys VCS
• Conduct code and functional coverage analysis
• Debug and solve complex technical issues
• Collaborate with cross-functional teams to ensure project success

Benefits

• Onsite work in a vibrant environment in Mountain View, CA
• Opportunity to work with industry-standard tools and methods
• Potential for professional growth and skill enhancement
• Engagement in a collaborative and innovative team culture