FPGA Hardware Design EngineerSiemens DISW is the world leader in the Electronic Design Automation (EDA) market. Our company offers software and hardware design solutions that enable companies to quickly develop leading-edge electronic products by optimizing their costs and performance. Mentor Graphics was acquired by Siemens in 2017. With the widest range of products in the industry, Mentor Graphics is the only company in the EDA market to offer an integrated software solution. Its subsidiary, based in Wilsonville Oregon, develops proprietary technologies to reduce the time needed to design integrated circuits and SoC (prototyping, validation and debugging). As part of its development, the company wishes to strengthen the R&D team by integrating a FPGA prototyping debug and runtime infrastructure development engineer.
Position Overview:Exciting opportunity in Mentor's FPGA Prototyping R&D team. The Wilsonville team focuses on debug infrastructure and hardware platform infrastructure support for Mentor's FPGA prototyping software system and hardware platform. As a contributing engineer, you will participate in the design, specification, implementation, test, and maintenance of software and FPGA RTL hardware IP for our products.
Specific technical responsibilities include:
- Design, implementation and maintenance of IP blocks in Verilog
- Validation and testing using simulation and FPGA hardware boards
- Development and testing of related software components
- RTL synthesis with timing and physical constraints, capacity and performance goals - Specifically, executing Xilinx Vivado and Intel PSG Quartus flows
- Hardware system performance analysis, debug and tuning
- Customer support to ensure smooth deployment of developed features
The candidate should be a self-motivated team player who is skilled and productive at quality-oriented and performance-oriented software and hardware engineering. The candidate will work in a world-wide distributed team. Some periodic travel to R&D or customer sites is expected in future (when Covid-19 pandemic conditions ease).
Education:Skills:- RTL design with SystemVerilog, Verilog, or VHDL
- ASIC and/or FPGA implementation and flows (synthesis, place & route)
- Experience with Xilinx Vivado or Intel PSG Quartus flows
- RTL IP, Xilinx Vivado IP, Intel PSG Quartus IP, and design reuse
- RTL simulation, verification, debug, and timing analysis
- Programming languages C/C++ and Python
- Data structures and algorithms
- Linux OS
You'll Benefit FromSiemens offers a variety of health and wellness benefits to our employees. Details regarding our benefits can be found here: https://www.benefitsquickstart.com/siemens/index.html
The pay range for this position is 90,000 - 162,000 annually with a target incentive of 3-5% of the base salary. The actual wage offered may be lower or higher depending on budget and candidate experience, knowledge, skills, qualifications, and premium geographic location.
