FPGA Implementation Engineer (JR)

As an FPGA Implementation Engineer in our mixed-signal audio development team, you will perform the synthesis of ASIC designs onto FPGA platforms and ensure the quality of the design. You will work on complex FPGA prototyping systems and will help drive improvements in prototyping methodology across the division. Responsibilities: • Help deliver FPGA Platforms to internal groups to enable software development, and hardware-software pre-silicon validation. • Porting ASIC-specific code and models into FPGA-friendly models. • Define and run functional tests to prove the FPGA builds prior to FPGA distribution. • Perform FPGA synthesis, Implementation and Static Timing Analysis for complex ASIC designs. • Develop and maintain smoke tests to guarantee the quality of the deliverables from revision to revision. • Test the digital chip RTL from a user perspective on FPGA platforms. • Design and implement equivalent analog models to model the final ASIC analog front end. • Introduce model-based designing methods with the help of Simulink or Matlab framework and representation. Required Skills and Qualifications: • Master's degree in Electrical Engineering, Computer Science, or similar field and 3+ years of directly related experience. • Experience using FPGAs and an understanding of how FPGA design differs from ASIC design. • Proficient in operating the simulation and modeling equipment including the design tools. • Knowledge of Verilog, System Verilog, and digital design concepts. • Verification/validation techniques and methodologies, including strong debugging skills. • Familiar with common on-chip bus protocols such as AMBA (AXI, AHB, APB) and communication protocols such as SPI, I2C, I2S, and UART. • Experience with Scripting for Hardware development (Python/Tcl) Preferred Skills and Qualifications: • Experience in FPGA flows - Synthesis, Place & Route, and Timing closure, with emphasis on Synopsys Synplify and Xilinx Vivado. • Understanding of common FPGA primitives such as memories, I/O pads, BUFG, and MMCMs. • Experience with Object-oriented programming (OOP) in Python. • Experience with Floorplanning and advanced timing closure techniques. • Familiar with lab equipment such as Oscilloscope, Signal Generators and Logic Analyzers. • Solid documentation, communication, and interpersonal skills. • Work to tight and variable time scales.