FPGA Engineer

Bolt Graphics

$150K — $220K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelors or Masters in Computer or Electrical Engineering or equivalent.
  • Proficient in System Verilog and C/C++ programming.
  • Experience with Xilinx Versal and Alveo platforms.
  • Knowledge of QSFP+ fiber communication and encoding strategies.
  • Familiarity with waveform analysis for debugging and optimization.
  • Experience creating custom interfaces with AXI protocol.
  • Skilled in addressing timing violations through constraints and analysis.

Responsibilities

  • Develop FPGA systems leveraging System Verilog.
  • Debug and troubleshoot design issues effectively.
  • Utilize Xilinx Vivado for comprehensive FPGA development.
  • Set up and analyze signals with ILA for enhanced debugging.
  • Document RTL designs following established standards.
  • Collaborate with team members across various time zones.

Benefits

  • 100% coverage of Medical, Dental, & Vision premiums.
  • Employee stock options available.
  • 401(k) matching program.
  • Provision of work-from-home hardware.
Full Job Description
About the role:

We are seeking a highly skilled FPGA Engineer who is fluent in System Verilog and is an expert user of Xilinx (acquired by AMD) FPGAs.

What you'll do:

  • Develop and design FPGA systems using System Verilog
  • Debug / Troubleshoot issues in the design
  • Utilize Xilinx Vivado for FPGA development
  • Set up and analyze signals using ILA for debugging purposes
  • Document RTL using standard practices
  • Communicate with team members across different time zones

Qualifications:

  • Bachelors, Masters in Computer Engineering, Electrical Engineering, or equivalent.
  • Programming: System Verilog, C/C++
  • Experience with the Xilinx Versal platform
  • Experience with the Xilinx Alveo platform
  • Experience with QSFP+ fiber communication and encoding strategies
  • Experience with waveform analysis for debugging and optimization
  • Experience with GTY/GTM
  • Experience with using and creating custom interfaces using AXI protocol
  • Experience with fixing timing violations through constraints and logic critical path analysis
  • Ability to create testbenches to verify functionality of RTL
  • Advanced debugging features and signal analysis via ILA.
  • Ability to read technical documents/standards and design hardware to follow those standards
  • Startup experience


Compensation Range: $150,000-$220,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.

Benefits:

  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match
  • WFH Hardware


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