5+ years of hands-on experience in Verilog/SystemVerilog RTL design
Proven background in Control Path design
Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI)
Local to the area
Preferred: Experience with Ethernet Data Path architecture and design
Preferred: Proficiency in Python, Tcl, or general scripting for EDA tool automation
Responsibilities
Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code
Execute the full FPGA development flow, including synthesis and timing closure
Collaborate with hardware and software teams for system integration
Participate in peer RTL code and PCB design reviews
Develop scripts to automate FPGA design workflows
Benefits
Collaborative work environment with cross-functional teams
Opportunity to work on cutting-edge networking technologies
Hands-on experience with advanced FPGA design and verification
Access to professional development in modern Ethernet protocols
Involvement in the full design lifecycle from concept to deployment
Full Job Description
Job Description
Who You'll Work With
You will work closely with cross-functional hardware, software, and manufacturing engineering teams to innovate new system architectures and drive FPGA development from initial concept to final delivery.
What You'll Do
Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and bleeding-edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments.
As a core member of the FPGA Design and Verification team, you will drive the development of high-performance control path FPGAs powering Arista's flagship data center platforms. You will own the full design lifecycle-from gathering architectural requirements and reviewing board schematics to executing rigorous verification, leading system bring-up, and supporting production deployment.
Responsibilities:
RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
System-Level Integration: Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
Design & Architecture Reviews: Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
Toolchain Automation: Develop AI-skills, Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows
Concepts & Skills You Will Gain
Switching Architectures: Master data and control path architectures in modern Ethernet switches, alongside critical I/O interfaces (e.g., PCIe, Interlaken, Ethernet PHY/MAC, SMBus, SPI, MDIO, JTAG).
Networking Protocols: Gain hands-on experience with Ethernet-based protocols, including PTP, sFlow, and PoE.
Practical FPGA Engineering: Learn to navigate real-world design challenges, including tight timing closure, resource optimization, clock domain crossing, and complex state machine design.
Multi-Vendor Ecosystems: Develop expertise across major vendor FPGA architectures, toolchains, and IDEs.
Cross-Functional System Design: Build skills in interpreting complex PCB schematics, running advanced simulation frameworks, and solving multidisciplinary hardware/software challenges.
Qualifications
5 years or more of hands-on experience in Verilog/SystemVerilog RTL design.
Proven background in Control Path design.
Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
Local to the area
Preferred:
Experience with Ethernet Data Path architecture and design.
Hands-on experience with Streaming Bus interfaces (e.g., AXI-Stream).
Background in FPGA resource management and timing closure.
Proficiency in Python, Tcl, or general scripting for EDA tool automation.
Lab Debugging & Validation: Utilize logic analyzers (LA), oscilloscopes, and vendor-specific debug tools for lab bring up, debug, and validation.
About Arista Networks
Arista Networks is a computer networking company headquartered in Santa Clara, California. The company designs and sells multilayer network switches to deliver software-defined networking solutions for large datacenter, cloud computing, high-performance computing and high-frequency trading environments. Arista Networks was founded in 2004 by former Cisco Systems engineers and is led by CEO Jayshree Ullal. The company went public in 2014 and is traded on the New York Stock Exchange under the ticker symbol ANET.
