Important Notes: - VHDL Experience is required for all candidates to be considered.
- Looking for mid-senior level folks
We've determined which skillsets are most beneficial for this role. These skills are listed first below as the Must Haves and Nice to Haves our hiring team highly prefers. Below that you'll find the standard job description for this opportunity.
Must Haves: - Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
- Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
- Big Plus
- Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
- Mentor EDA CDC/Lint/AC/RDC
- At least 3-year experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs
- Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
- Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado
- Excellent Analytical/Debug skills
- Good verbal, written, and presentation skills
- US Citizenship required
- High Level Synthesis (HLS) with Vivado,
- Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
- Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).
Nice to Haves:N/A
Job Description: Develop architectures for the implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
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