Role SummaryRivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2027 and 2029. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions.
If you are not pursuing a degree, please see our full time positions on our Rivian careers site. Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements.
Our Spring Co-op program runs from Jan-Aug 2027. In order to be considered for this role, you must be available to work onsite, full time (40 hours per week), for the entire duration. If you're unable to work during the spring semester, please instead apply to our Summer Internship Program.
No Visa SponsorshipIn this role, you will focus on working closely with the Silicon Development team here at Rivian. Technical Program Managers are responsible for driving the end-to-end execution of Rivian's SoC (System-on-Chip) development programs from early architecture through tapeout, bring-up, and production aimed at ADAS hardware.
Responsibilities- Own the integrated silicon program plan-including architecture definition, RTL (Register-Transfer Level) design, Design Verification (DV) milestones, physical design (PD) closure, DFT (Design for Test), tapeout, and post-silicon bring-up.
- Cross-Functional Coordination: Partner tightly with Architecture, RTL, DV, Firmware, Software, Package/Board, and Supply Chain teams to eliminate bottlenecks and align hardware software co-design.
- Vendor & Foundry Management: Coordinate external partners, including semiconductor foundries, IP vendors, ASIC design services
- Risk & Dependency Tracking: Identify critical-path schedule risks, monitor design maturity, track coverage metrics, and maintain clear escalation paths.
- Leadership Communication: Act as the primary liaison between engineering teams and executive leadership, translating complex technical trade-offs into actionable decisions.
Qualifications- Must be currently pursuing a bachelors, masters, or PhD degree at an accredited university
- Actively pursuing a degree or one closely related in Electrical/Computer Engineering or Computer Science
- Experience in pre-silicon (RTL/DV/Tapeout) or post-silicon (Bring-up/Operations/Supply Chain) is a plus
- Good communication skills
- Experience with JIRA or other similar tracking workflows for cross-functional tracking and alignment.
- Self motivated and willing to learn and adapt to changing priorities.
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Pay DisclosureThe salary range for this role is $45.00-51.00 per hour for Palo Alto based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee's position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.
We offer a comprehensive package of benefits including but not limited to paid vacation, paid sick leave, and medical insurance benefits. Internship positions are not eligible for retirement benefits. More information about benefits is available at rivianbenefits.com.
You can apply for this role through careers.rivian.com (or through internal-careers-rivian.icims.com if you are a current employee). There is no fixed deadline for this application; applications are accepted on an ongoing basis until the role is filled or the opening is no longer needed.
Please note that we are currently not accepting applications from third party application services. 
