Job Description:Join the dsPIC Microcontroller Business Unit, IP Verification Engineering team as Engineer II-Verification, doing IP level verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation (UVM tests), debugging, signoff evidence, and lifecycle support. This role is best suited for candidates with 2.5-5 years of relevant experience in IP design verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation, debugging, signoff evidence, and lifecycle support.
In this role, you will independently execute defined assignments and structured troubleshooting, partner with cross-functional teams (architecture, design, product development , validation, and application) across the USA, India, and other global corporate teams to deliver robust verification results, timely project execution, and continuous improvement.
Responsibilities:- Architect, develop, and maintain UVM based verification environments and/or Formal verification environments.
- Collaborate with architecture, designer, validation, and applications teams to verify IP and product requirements.
- Develop and maintain verification plans, test strategies and testbenches.
- Develop constraint random tests and testbench, assertions and coverage, analyze coverage metrics and drive coverage closure.
- Develop Formal properties, analysis proof results and drive Formal coverage closure.
- Configure, execute, and maintain UVM simulation and/or Formal regressions.
- Debug failures in RTL and testbench, perform root-cause analysis, and collaborate with design and architecture teams to resolve the defects.
- Leverage AI-assisted and machine-learning based automation to improve verification quality, accelerate development and debugging, and reduce verification cycle time.
Requirements/Qualifications:Minimum qualificationsBachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, Engineering, or a related field with 2.5-5 years of relevant experience in design verification, UVM and/or Formal testbench architecture, modeling, simulation, coverage, regression, debugging, signoff evidence, and lifecycle support.
Qualified candidates should demonstrate verification architecture, modeling, and simulation, UVM and Formal testbench development, coverage analysis, structured debugging, AI/ML automation, technical documentation, and cross-functional influence.
Successful candidates are expected to demonstrate:- Employment stability, reliability, and sustained accountability in prior roles.
- Effective teamwork and cross-functional collaboration.
- Integrity and accuracy in representing qualifications, experience, and credentials.
Preferred Qualifications:- Hands-on experience with UVM-based simulation and/or Formal verification methodologies and tools.
- Strong proficiency in System Verilog language, constrained-random verification, assertions, and coverage.
- Experience developing and maintaining IP level and SoC level verification environments.
- Experience with simulation, regression execution, coverage analysis, debug, verification signoff, and lifecycle support.
- Experience with verification automation and scripting using Python or Perl.
- Experience with AI assisted technologies to improve verification productivity, quality, and driver faster coverage closure.
- Strong understanding of digital design concepts, RTL fundamentals, and ARM or common SoC architectures.
Travel Time:0% - 25%
Physical Attributes:Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:80% Sitting, 10% Walking, 10% Standing
