Digital IC Design Verification Engineer

We're looking for a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECS What you'll do: - Work as part of a multi-disciplinary team designing display ICs for AR - Work closely with digital and analog logic, circuit and physical design engineers & other custom layout engineers - Perform cell and block layout of Analog and Mixed-Signal circuit functions, meeting design rules and performance - Craft reusable scripts and methodologies that help automate design flow, repeatability and efficiency - Implement circuit layout strategies for optimal area, performance and power goals. - Support IC floor planning and place & route of full chip digital designs with digital and analog IP - Provides schedule, and cost inputs to program management - Create and present design documentation for internal design reviews - Execute parasitic extraction of circuit layout and iterate design improvements Knowledge, Skills & Abilities: - Strong working knowledge of custom (transistor-level) layout, including matching techniques - Strong working knowledge of Cadence Virtuoso (Layout and Schematic) tool suite - Strong working knowledge of Mentor/Siemens Calibre tool suite (DRC, LVS, Extraction) - Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts in Linux environment - Experience and capability to execute project tape out verification including DRC, ERC and LVS - Extensive understanding of signal integrity, reliability, layout effects (EM, IR drop) and other considerations - Knowledge of tool flows and techniques for achieving foundry DFM requirements - Track record of prior detailed design and custom layout experience of various types of designs such as SRAM, level shifters, IO design (ESD, latch-up), PLLs, Bandgaps, ADCs, DACs and amplifiers. Minimum Qualifications: - BSEE or relevant years of experience - 5+ years in directly applicable work performing custom layout - Optional - see preferred Qualifications Preferred Qualifications: - Detailed understanding of 22nm and below CMOS foundry design node rules and requirements. - Experience with both Analog and Memory layouts - Excellent technical, documentation and verbal skills working with engineering and management teams - Knowledge of ASIC IC test and characterization - Understanding of digital design and place and route principles "Default Together" Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster, reinforce our values, and serve our community, customers and partners better through dynamic collaboration. To reflect this, we practice a "default together" approach and expect our team members to work in an office 4+ days per week. Our Benefits: Snap Inc. is its own community, so we've got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy, on your own terms. Our benefits are built around your needs and include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that let you share in Snap's long-term success! Compensation In the United States, work locations are assigned a pay zone which determines the salary range for the position. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions. The starting pay may be negotiable within the salary range for the position.These pay zones may be modified in the future. Zone A (CA, WA, NYC): The base salary range for this position is $173,000-$259,000 annually. Zone B: The base salary range for this position is $164,000-$246,000 annually. Zone C: The base salary range for this position is $147,000-$220,000 annually. This position is eligible for equity in the form of RSUs.