Design Verification Engineer- AI Accelerator Lead

Velaura

$200K — $350K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 8+ years in high performance compute or complex digital design verification.
  • Strong understanding of LLMs, including transformer structures and inference data flow.
  • Familiarity with GEMM/GEMV operations and hardware mapping.
  • Proficient in SystemVerilog, UVM, C, and C++ for verification processes.
  • Experience in creating reference models using C, C++, or Python.
  • Knowledge of numerical formats and precision tradeoffs (FP16, BF16, FP8, INT8).
  • Proven ability to independently oversee design blocks from testing to coverage closure.

Responsibilities

  • Own the verification of custom AI acceleration units, focusing on matrix and vector compute engines.
  • Collaborate with architects to translate microarchitecture intent into detailed test and coverage plans.
  • Develop portable verification environments using SystemVerilog, UVM, C, and C++ with complete stimulus and checking.
  • Create reference models for GEMM and GEMV and validate hardware outputs against these models.
  • Audit data flow operations like operand staging, tiling, and accumulation for accelerators.
  • Ensure accuracy in precision, rounding, and quantization against architecture specifications.
  • Assess throughput, latency, and performance metrics against strict targets under various workloads.
  • Manage regressions and utilize bug and coverage metrics to support design and environment enhancements.

Benefits

  • Comprehensive medical, dental, and vision coverage.
  • Paid time off and flexible work arrangements.
  • Professional development opportunities for growth.
  • Equity participation in company success.
  • Commitment to pay equity and transparency.
Full Job Description
Role Overview

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role focuses on our AI acceleration units. We are designing custom compute engines from scratch to deliver industry leading inference performance at best in class energy efficiency, and every gain has to come inside a tight power envelope. You will own verification of the hardware that makes those numbers real, where correctness means numerical behavior as much as protocol.

Responsibilities
  • Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
  • Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
  • Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
  • Develop reference models for GEMM and GEMV operations and compare hardware results against them.
  • Verify accelerator data flow including operand staging, tiling, accumulation and result writeback.
  • Verify precision, rounding and quantization behavior against the architecture specification.
  • Verify throughput, latency, utilization and performance per watt against aggressive targets under representative LLM and vision workloads.
  • Execute regressions through design and environment bring up, track progress using bug and coverage metrics, and support emulation and pre silicon bring up with the compiler and runtime teams.


Required Qualifications
  • 8 or more years verifying high performance compute or complex digital designs.
  • High level understanding of LLMs including transformer structure and inference data flow.
  • Knowledge of GEMM and GEMV operations and how they map onto hardware.
  • Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
  • Experience building or using reference models in C, C++ or Python.
  • Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
  • Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
  • BS or higher in Computer Engineering, Electrical Engineering or Computer Science.


Preferred Qualifications
  • Prior experience porting LLM or neural network models to RTL and verifying them.
  • Experience verifying a custom accelerator developed from scratch rather than an integrated third party IP.
  • Familiarity with systolic arrays, tensor cores, attention, KV cache or mixture of experts hardware.
  • Experience with PyTorch, ONNX or compiler and runtime stacks for accelerators.
  • Experience with formal verification, gate level simulation or silicon bring up.
  • Exposure to performance modeling, power analysis, profiling and workload characterization.
  • Familiarity with robotics, drones, autonomous vehicles or edge AI systems.
  • Experience using AI assisted verification workflows to improve productivity and coverage.


$200,000 - $350,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

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