Design Verification (DV) Engineer

DensityAI

$200K — $300K *
Enterprise Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Expert-level proficiency in SystemVerilog for RTL reading and verification
  • Experience building or significantly extending UVM environments
  • Hands-on experience with logic simulation tools like Synopsys VCS or Cadence Xcelium
  • Proficient in waveform debugging using Synopsys Verdi or similar tools
  • Solid understanding of coverage-driven verification and constrained-random testing techniques
  • Strong communication skills to report and track bug resolutions

Responsibilities

  • Build the UVM verification environment for the custom accelerator
  • Write directed and constrained-random tests for various system components
  • Debug RTL mismatches using waveform analysis and troubleshooting
  • Drive functional coverage closure, tracking progress against goals
  • Develop assertion-based verification monitors for protocols
  • Validate ISA-level correctness by checking generated code execution
  • Establish and maintain a regression testing infrastructure

Benefits

  • Medical, dental, vision insurance
  • 401(k) retirement savings plan
  • Standard paid time off (PTO)
  • Equity grant opportunities
  • Immigration support for work authorization
Full Job Description
About the role

We're looking for an experienced Design Verification engineer with at least 5 years of pre-silicon verification experience in end to end verification for complex IP, subsystems, and/or SoC system level verification from plan to functional closure. This is a senior individual-contributor role and you'll partner closely with our HW-design and software teams, driving DensityAI's AI accelerator program from first silicon through scale-out.
What you'll do
  • Own an entire testing domain based on your expertise
  • Develop end to end testing strategy from IP to SOC-level and to emulation for our AI accelerator silicon
  • Use and develop AI-assisted tool flows to accelerate verification and emulation timeline
What we're looking for
  • 5+ years of experience in one or more of the following:
    • Block Level/Sub System Verification
    • CPU Subsystem/IP integration
    • SoC/full-chip Verification
    • Emulation testing
    • DMA/NoC Verification
    • Multi-SoC/Die to Die protocol verification
  • Debug for functional closure of complex design or SOCs
  • Proven records on end-to-end pre-silicon verification ownership and deliverables
  • Strong Interest in optimizing Verification techniques and life cycle using the latest agentic/AI assisted flows
  • Exceptional abilities in analyzing and understanding specification from both hardware and software perspectives
  • Well-versed in UVM methodology and testbench architecture
  • Ability to define clear goals and milestones to meet aggressive timelines and quickly adapt to a dynamic design life cycle
  • Self driven and passionate, with a strong sense of respectful team collaboration
  • Flexible Mindset to jump in and contribute to multiple domains within verification as needed
  • (Optional) RISC-V, formal verification, emulation platforms (Palladium, Veloce, or equivalent), or post-silicon bring-up
Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

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