Location: Richardson, TX We are seeking a highly motivated Design Lead to lead the architecture, design, integration, and execution of next-generation HBM and advanced memory products. The successful candidate will drive multi-functional collaboration across Design, Verification, Layout, CAD, Product Engineering, and Technology Development teams to deliver high-quality silicon on aggressive schedules. Key Responsibilities • Lead the design and execution of sophisticated memory subsystems and top-level integration activities. • Own design planning, technical decision-making, risk assessment, and schedule execution. • Coordinate with architecture, verification, layout, DFT, and product engineering teams to ensure design quality and manufacturability. • Review design specifications, microarchitecture documents, and implementation plans. • Drive memory array design, including address decoders and data path, internal power supplies, and custom circuit design activities depending on project needs. • Lead design reviews and drive issue resolution across organizations. • Guide engineers who are developing their skills and provide technical leadership to project teams. • Define and improve building methodologies by applying AI-enabled tools, automation, and guidelines. • Support silicon bring-up, debug, characterization, and yield improvement activities. • Communicate project status, risks, and mitigation plans to management and collaborators. Required Qualifications • BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. • 10+ years of semiconductor design experience (adjust per internal leveling guidelines). • Demonstrated experience leading complex IC development programs. • Strong understanding of digital and/or custom circuit design methodologies. Experience with: o Memory Array Design, address decoders, and Datapath architecture o Power Delivery and repair schemes o Verification and debug flows o DFT and silicon validation o Power, performance, area, and thermal optimization Preferred Qualifications • Experience with DRAM, DDR, HBM, LPDDR, or advanced memory products. • Experience leading global multi-functional teams. • Knowledge of advanced process nodes and design-for-manufacturing concepts. • Experience with Synopsys and Cadence implementation flows. • Familiarity with package integration, 2.5D/3D stacking, TSV, and advanced packaging technologies. • Consistent track record of successful product tape-outs. Leadership Expectations • Technical ownership of major product work. • Lead without direct authority across multiple organizations. • Influence architecture and technology decisions. • Mentor and develop engineering talent. • Drive execution excellence and accountability. Success Metrics • Delivery of build achievements on schedule. • Silicon quality and first-pass success. • Technical innovation and problem-solving. • Cross-functional collaboration effectiveness. • Mentorship and team impact.