Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic designs. This role involves characterizing standard and custom cells across multiple process technologies. These cover Micron internal nodes and external foundries, including TSMC. The role supports several HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will operate at the intersection of circuit design, EDA infrastructure, and silicon validation readiness, delivering robust, scalable, and high-quality characterization flows that directly impact timing closure, power modeling, and product quality across next-generation HBM programs. Responsibilites: - Develop and maintain scalable infrastructure for standard cell and custom cell characterization, including timing, power, noise, and signal integrity modeling. - Build reusable, automated flows to support multi-corner, multi-mode (MCMM) characterization across extensive PVT spaces, and enable robust Liberty model generation, validation, and regression frameworks to ensure high-quality results for downstream design and signoff flows. - Enable characterization across heterogeneous process technologies, including Micron internal nodes and external foundries such as TSMC. Address technology-specific challenges such as variability, layout-dependent effects, aging, and reliability, and drive consistent methodologies that allow seamless portability and standardization across multiple process nodes. - Support characterization requirements across diverse HBM product verticals, including core dies, multiple custom base dies, and emerging advanced HBM architectures. Collaborate closely with design teams to define characterization requirements for specialized circuit classes such as TSV interfaces, PHY-critical paths, and high-speed datapath elements, ensuring alignment with system-level performance and power targets. - Integrate characterization flows into broader design and verification ecosystems by partnering with design, verification, and CAD teams. Drive improvements in model accuracy, turnaround time, and silicon correlation while establishing standard processes for corner definition, quality metrics, and data consistency across IPs and programs. - Lead debug, validation, and continuous improvement efforts by root-causing mismatches between SPICE, extracted views, STA, and silicon behavior. Develop metrics, dashboards, and automated checks to ensure completeness, adaptability, and quality of characterization data, enabling reliable signoff and scalable deployment across future HBM programs. Minimum Qualifications: - Bachelors or Masters Degree in Electrical Engineering or a related field, along with strong fundamentals in CMOS digital and mixed-signal circuit design, device physics, and PVT variation. - Hands-on experience with standard or custom cell characterization flows-including Liberty modeling (CCS/ECSM or equivalent) and SPICE-based simulation-is essential. - A solid understanding of STA flows and timing libraries, combined with proficiency in scripting languages such as Python, Perl, or Tcl for automation, is required. - Experience in SiliconSmart or PrimeLib is required Preferred Qualifications: - Experience working across multiple semiconductor process technologies is highly desirable. - Experience in HBM, DRAM, or high-speed interface design is preferred, particularly in environments involving advanced foundry PDKs such as TSMC nodes. - Familiarity with high-speed PHY design, TSV-aware design considerations, and advanced modeling topics such as signal integrity, EMIR effects, aging, and reliability will differentiate candidates. - Prior exposure to infrastructure or methodology development-beyond just using characterization flows-is strongly valued, as this role requires building scalable solutions rather than implementing predefined flows. - Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.