BS or MS degree with 12+ years (Lead) or 5+ years (Individual Contributor) in clock design or custom circuit design.
Hands-on experience with clock dividers, deskew, duty-cycle correction, and clock-gating at advanced CMOS nodes.
Proven ability to construct low-skew, low-power clock distribution networks for high-frequency CPUs.
Strong SPICE simulation skills with knowledge of device physics and signal integrity in clock-path design.
Expertise in STA and clock timing signoff across Functional and DFT modes.
Track record of delivering clock networks/IP through tape-out with validated PPA metrics.
Excellent communication skills for collaboration with cross-functional teams.
Responsibilities
Architect and implement clock generation and distribution methodologies for high-frequency CPU cores.
Design and characterize custom clock circuits at the transistor level, ensuring PPA targets are met.
Oversee clock-network closure, including skew, latency, and jitter analysis using SPICE.
Collaborate with various teams to align clock source models and power-aware clocking methodologies.
Drive automation and best practices in clock-analysis tools and flows.
Benefits
Opportunity to work on cutting-edge clock design technologies.
Collaborative environment with cross-functional teams.
Access to advanced tools and methodologies for clock analysis.
Potential for professional growth in a high-impact role.
Full Job Description
As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following :
Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.
Design and characterize custom clock circuits at "transistor level": clock buffers and repeaters, dividers, deskew and duty-cycle correction, clock-gating and clock-mux cells meeting PPA targets across PVT corners.
Own end-to-end clock-network closure: SPICE-driven skew, latency, and jitter analysis, EM/IR and signal-integrity signoff on the clock grid, and STA correlation (OCV/AOCV/POCV) across Functional and DFT modes.
Partner with PLL/FLL, timing, power, CAD, physical design, and DFT teams aligning clock source models, jitter budgets, and power-aware clocking and drive Tools, Flows and Methodology (TFM), including clock-analysis automation and team-wide best practices.
MINIMUM QUALIFICATIONS
Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in clock design, clock distribution, and/or custom circuit design.
Hands-on transistor-level design experience with clock dividers, deskew and duty-cycle correction, clock-gating and mux cells at advanced CMOS nodes.
Proven experience constructing and analyzing low-skew, low-power clock distribution networks using H-tree, mesh, spine, and multi-source CTS for high-frequency CPUs.
Strong SPICE simulation and analysis skills, with solid grounding in device physics, RC delay, and signal integrity applied to clock-path design and verification.
Well-versed in STA and clock timing signoff including setup,hold,duty- cycle closure across Functional and DFT (Design for Test) modes.
Demonstrated track record delivering clock networks and/or clocking IP through tape-out, with silicon-validated PPA - frequency, skew, jitter, and power - in high-volume products.
Strong communication and collaboration skills, comfortable working directly with PLL, CAD, physical design, and foundry partner teams.
REQUIREMENTS - PREFERRED
Proficiency with PLL/FLL specifications, clock source modeling, skew estimation, jitter budgeting, and jitter/duty-cycle measurement.
Experience with power-aware clocking - clock gating, DVFS, clock-skipping, and resonant or mesh-based clocking strategies for clock-power reduction.
Deep understanding of clock-network signoff - EM/IR on the clock grid, dynamic voltage-drop-aware timing, crosstalk and noise, and Monte Carlo variation studies.
Experience with testchip clock development and benchmarking, and partnering directly with foundries on PDK bring-up and clock-device co-optimization (DTCO) at leading-edge nodes.
Familiarity with the full clock flow - architecture, circuit design, physical implementation of the clock network, and timing/model generation - at block and full-chip level.
Proficient in Python, Perl, or TCL to build and improve clock analysis, characterization, and methodology automation.
Experience using Agentic AI tools for productivity and automation.
