Role Overview

We are looking for a CAD & Engineering Infrastructure Lead to build and own the engineering platform behind Velaura's silicon development: the compute infrastructure, EDA ecosystem, integrated RTL-to-GDS release flow, and AI-assisted workflows that every design team depends on. This role owns flow release and qualification, design-flow CI/CD pipelines, multi-vendor EDA tool deployment, and EDA licensing, procurement, and vendor strategy; domain design methodology and flow content stay with the functional teams: RTL, verification, DFT, physical design, and packaging. The ideal candidate is hands-on setting up and maintaining integrated RTL-to-GDS flow environments, understands engineering compute infrastructure and license management at scale, and has a practical view of where AI creates measurable leverage in chip development. Above all, this is someone who measures success by how productive everyone else is.

Responsibilities
• Define and drive Velaura's engineering infrastructure requirements covering compute, storage, job scheduling, security, backup, disaster recovery and cloud in partnership with stakeholders.
• Lead AI adoption across engineering functions including RTL, verification, DFT, physical design, packaging, software, and CAD itself. Identify where AI-assisted workflows create measurable leverage and drive them from pilot to standard practice.
• Own design-flow CI/CD pipelines including orchestration, flow-release qualification, and result/QoR dashboards
• Provide the compute, capacity, and deployment support that functional regressions run on, scaling to thousands of jobs per week; teams own their regression content, triage, and pass/fail criteria, and this role makes sure the infrastructure underneath never becomes the bottleneck.
• Own flow release process end to end: assemble team-owned flow content into qualified releases, regression-test before deployment, and manage versioning, cadence, and rollback - keeping handoffs from RTL through synthesis, place-and-route, and signoff consistent.
• Lead the deployment, and integration of EDA tools across multiple vendors, balancing productivity, quality, flexibility, and cost.
• Own EDA licensing strategy, vendor relationships, procurement, budgets, IP administration, and license compliance.
• Build and operate the platform behind AI-assisted engineering-model access, agentic tooling, compute capacity, and data pipelines-with the security and IP guardrails required to apply AI to proprietary design data safely, measuring productivity impact and retiring what doesn't pay off.

Required Qualifications
• Deep understanding of the complete ASIC development lifecycle, from architecture and RTL through tapeout-enough to be a credible partner to every functional team.
• Experience owning CAD and infrastructure across multiple successful SoC programs.
• Hands-on experience setting up and maintaining an integrated RTL-to-GDS flow environment-tool and version management, foundry and IP collateral integration, and flow release and qualification across concurrent projects.
• Strong understanding of engineering compute infrastructure: distributed scheduling (LSF, Slurm, or equivalent), storage systems, networking, cloud environments, and license management at scale.
• Hands-on experience with EDA ecosystems from multiple vendors such as Synopsys, Cadence, and Siemens EDA.
• Strong knowledge of version control, CI/CD platforms, and the compute and storage patterns behind high-volume regression workloads, along with reproducible engineering practices.
• Excellent scripting and automation skills using Python, Tcl, Bash, or similar.
• Experience evaluating and deploying AI-assisted engineering tools and workflows, with a practical view of where they create leverage in chip development.
• Excellent communication skills and the ability to influence senior technical leaders across disciplines.

Preferred Qualifications
• Experience scaling infrastructure in an early-stage semiconductor company.
• Experience with advanced technology nodes with leading foundries.
• Experience building or operating agentic AI systems, LLM-based tooling, or AI-native design automation.
• Experience supporting chiplet-based designs or advanced packaging.

$200,000 - $500,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.