10+ years of digital design verification experience
3+ years managing or leading verification teams
Track record of completing two or more full block/system verification cycles
In-depth knowledge of VLSI verification flows and algorithmic model interfaces
Expertise in SystemVerilog and UVM
Experience in block, cluster, and full chip verification
Strong problem-solving and debugging skills
Excellent leadership and communication abilities
Responsibilities
Lead and mentor verification engineers to meet project milestones
Define and execute verification strategies for complex systems
Develop robust and reusable verification environments using SystemVerilog and UVM
Review and approve verification plans and testbenches
Drive functional and coverage-based verification across verification cycles
Collaborate with design engineers to debug functionality issues
Ensure effective resource allocation and project planning
Foster a culture of technical excellence within the team
Report verification progress and issues to senior management
Benefits
Opportunity to work with a well-funded start-up
Engagement in cutting-edge technology in high-speed communication
Culture of continuous learning and innovation
Potential for career advancement with a focus on technical excellence
Collaborative environment with cross-functional teams
Full Job Description
Description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects.
Requirements
Key Responsibilities
Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables.
Define and execute verification strategies and plans for complex digital blocks and systems.
Oversee the development of robust and reusable verification environments using SystemVerilog and UVM.
Review and approve verification plans, testbenches, and coverage metrics.
Drive functional and coverage-based verification across multiple block/system verification cycles.
Collaborate with design engineers to debug and resolve functionality issues.
Ensure effective resource allocation and project planning to achieve optimal results.
Foster a culture of technical excellence, continuous learning, and innovation within the team.
Report verification progress, issues, and risks to senior management and other stakeholders.
Required Qualifications
10+ years of experience in digital design verification-a must.
3+ years of experience managing or leading verification teams.
Proven track record of completing two or more full block/system verification cycles.
In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW.
Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM).
Experience in block, cluster and full chip verification levels.
Strong problem-solving skills and the ability to debug complex functionality issues.
Excellent leadership, communication, and organizational skills to manage and inspire a team.
Preferred Qualifications
Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes.
Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
Familiarity with formal verification techniques and tools.
Background in system-level verification or post-silicon validation.
Experience with project planning tools and methodologies for effective team management.
