Qualifications

• Master's degree desired; Bachelor's degree in Computer Science or Electrical Engineering required.
• 8+ years of relevant experience in ASIC verification.
• Experience in developing and implementing test plans for complex ASICs at block or sub-chip levels.
• Proficient in System Verilog and scripting languages like Python.
• Intimate knowledge of UVM methodology is essential.
• Familiarity with assertions, functional coverage, and formal verification tools.
• Strong problem-solving and communication skills, with a preference for teamwork in diverse environments.

Responsibilities

• Develop and verify leading-edge SoCs using advanced ASICs and FPGAs.
• Create System Verilog/UVM-based protocol and traffic generators/checkers.
• Design test plans based on functional and standards requirements.
• Collaborate with experts across various domains for optimal solutions.
• Work with system engineers and HW/SW teams to resolve technical challenges.
• Support hardware/software bring-up and debugging processes.
• Lead a team or work independently to achieve project goals.

Benefits

• Opportunity to work on cutting-edge technology in ASIC and FPGA development.
• Collaborative environment with experts from various fields.
• Potential for leadership roles in project execution.
• Engagement in a diverse and geographically distributed team.
• Access to advanced tools and methodologies in ASIC verification.