Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field (must be completed before joining)
PhD in Computer Science, Computer Engineering, or a relevant technical field (or equivalent practical experience)
Experience in micro-architecture and RTL development for complex control and data path IPs
Proficiency in RTL development using Verilog, SystemVerilog, and HLS
Familiarity with data path development and SoC micro-architecture
Responsibilities
Explore architecture options for ASIC designs
Develop micro-architecture specifications
Identify, select, and integrate soft and hard IPs
Collaborate with verification and emulation teams on test plans and debugging
Work with implementation teams to ensure design meets timing and power requirements
Benefits
Opportunity to work on cutting-edge technology in machine learning and network acceleration
Collaborative work environment with cross-functional teams
Access to advanced tools and resources for ASIC design
Potential for career growth within a leading tech company
Engagement in innovative projects that impact global technology trends
Full Job Description
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Responsibilities
Architecture exploration • Micro-architecture development • Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug • Collaboration with implementation team to close the design on timing and power
Minimum Qualifications • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta • Currently has, or is in the process of obtaining a PhD degree in computer science, computer engineering, a relevant technical field, and/or equivalent practical experience • Experience in micro-architecture and RTL development for complex control and data path IPs or experience in SoC micro-architecture, design and integration • RTL development using Verilog, SystemVerilog and HLS
Preferred Qualifications • Experience in data path development • Experience in CPU, NOC, Memory and Peripheral Subsystems • Experience with Synthesis, Timing Closure and Formal Verification Methodology
