Full Job Description
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Responsibilities
Architecture exploration
• Micro-architecture development
• Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power
Minimum Qualifications
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
• RTL development using Verilog, System Verilog and HLS
Preferred Qualifications
• Experience in CPU, NOC, Memory and Peripheral Subsystems
• Experience with Synthesis, Timing Closure and Formal Verification Methodology
• Master's or PhD degree in Electrical Engineering, Computer Science or related areas
• Experience in data path development
