Position OverviewWe are looking for a Senior ASIC Diagnostics Engineer to drive post-silicon bring-up, debug, and validation of next-generation high-performance ASICs. This role focuses on building diagnostic infrastructure, automation frameworks, and debug tools to validate ASIC functionality across SERDES, high-speed interfaces, and packet processing pipelines.
The ideal candidate is hands-on, software-driven, and comfortable debugging across RTL, firmware, and silicon.
Key Responsibilities- Develop diagnostics for early silicon validation and debug
- Lead bring-up of ASIC silicon on characterization and validation platforms
- Validate power, reset, and clocking sequences, along with register access and initialization flows
- Design and build Python-based diagnostic frameworks for register access, configuration management, and test orchestration; convert debug procedures into automated test flows
- Develop diagnostics for SERDES links (training, BER, eye margining), Ethernet, PCIe, and UCIe / chiplet interfaces
- Use SDKs and internal tools to generate traffic, verify data path correctness, and validate counters and statistics
- Integrate and correlate behavior across RTL verification, emulation platforms, and silicon; develop correlation tools and methodologies
- Perform deep debug across ASIC logic, interfaces, and firmware interactions; isolate functional mismatches, timing/clocking issues, and protocol failures
- Develop automated diagnostics and integrate into regression frameworks and continuous validation pipelines
Required Qualifications- Bachelor's with 10+ years or Master's with 5+ years of relevant experience
- Strong experience in ASIC bring-up / post-silicon validation and hardware-software debug
- Strong programming skills in Python (mandatory), along with C/C++ and scripting
- Experience building diagnostic frameworks, automation tools, and test orchestration systems
Preferred Qualifications- Experience with SERDES , UCIe / chiplet architectures, or networking ASICs
- Familiarity with packet processor SDKs and emulation platforms
- Experience with BER testing tools and SERDES tuning/margining
- Exposure to CI/regression infrastructure for silicon validation
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The pay range for this role is:
180,000 - 250,000 USD per year (San Francisco Bay Area)
