Advanced Micro Devices, Inc

ASIC Design Verification Engineer

Advanced Micro Devices, Inc • $110K — $130K *
Rochester, NY 14609In-Person
Telecommunications & Hardware
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • Bachelor's or Master's in Electrical/Computer Engineering
  • Experience with system-level or SOC-level verification of mixed-signal devices
  • Real-number modeling (RNM) experience using SystemVerilog or Verilog-AMS
  • Proven record in formal verification and assertion-based verification methodologies
  • Strong development skills in SystemVerilog and UVM testbench creation
  • Capability to mentor junior engineers and lead verification reviews
  • Experience with post-silicon bring-up and debug processes

Responsibilities

  • Own the verification strategy and coverage closure for mixed-signal power management ICs
  • Define and track functional and code coverage goals, reporting status to the project team
  • Drive the team towards verification signoff criteria before tape-out
  • Maintain and enhance regression infrastructure and results reporting
  • Execute system-level verification, including power state transitions and fault scenarios
  • Build and maintain SystemVerilog/UVM testbench components and sequences
  • Collaborate with Analog and RTL designers for design reviews and debugging efforts

Benefits

  • Comprehensive AMD benefits package
  • Opportunity for professional development and mentorship
  • Collaboration with diverse engineering teams
  • Access to cutting-edge verification technologies
  • Involvement in impactful projects within the semiconductor industry
Full Job Description
THE ROLE:

The focus of this role is to own the verification strategy and coverage closure for AMD's mixed-signal power management IP, driving system-level verification of the full SOC while also contributing block-level verification and RTL design.

THE PERSON:

You have a passion for finding bugs. You think in terms of coverage, corner cases, and what has not been exercised yet. You are comfortable reading RTL as well as writing testbenches, and you enjoy working at the boundary between digital and analog. You are a team player with excellent communication skills, strong analytical and problem-solving ability, and the persistence to chase an intermittent failure to root cause.

KEY RESPONSIBILITIES:

Verification Ownership & Coverage
  • Own the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC
  • Define functional and code coverage goals, track progress against them, and report verification status and readiness to the project team
  • Own verification signoff criteria and drive the team to coverage closure ahead of tape-out
  • Maintain and improve regression infrastructure, triage flow, and results reporting


System-Level Verification
  • Develop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic
  • Verify firmware-driven behavior in co-simulation of embedded firmware with RTL
  • Build and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level


Block-Level & Mixed-Signal Verification
  • Develop block-level test benches and coverage for digital blocks as project needs require
  • Verify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment
  • Partner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent


Collaboration & Design Support
  • Partner with RTL designers on design reviews, verification planning, and debug of failures to root cause
  • Contribute to SystemVerilog RTL design work across the team as needed
  • Support post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases
  • Work across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology


PREFERRED QUALIFICATIONS:
  • System-level or SOC-level verification ownership on a mixed-signal device
  • Real-number modeling (RNM) of analog blocks in SystemVerilog (wreal / nettype real), or experience with Verilog-AMS
  • SystemVerilog RTL design experience in an ASIC environment
  • Firmware/RTL co-simulation or hardware/software co-verification experience
  • Formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience
  • Post-silicon bring-up and debug experience
  • Experience mentoring engineers and leading verification reviews
  • Strong SystemVerilog and UVM testbench development skills, with ownership of verification for a block or subsystem through tape-out
  • Demonstrated experience defining verification plans and driving functional and code coverage to closure
  • Proficiency with simulation, coverage, and debug tools, and with regression automation
  • Ability to read and understand RTL and design specifications to independently derive test intent


ACADEMC CREDENTIALS:
  • Bachelors or master's in electrical/computer engineering


#LI-DP1

Benefits offered are described: AMD benefits at a glance.

This posting is for an existing vacancy.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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