5-7 years of experience in ASIC design engineering
Proven track record of ownership in advanced node tapeouts
Strong understanding of Power, Performance, and Area (PPA) optimization
Creative problem-solving skills for rapid design iterations
Experience with large die ASIC design preferred
Familiarity with AI chip design is a plus
Knowledge of multi-die and multi-chiplet architectures is advantageous
Responsibilities
Contribute to the design and development of A-0 and A-1 wafer products
Own specific blocks within the ASIC design process
Collaborate with cross-functional teams to enhance design methodologies
Implement strategies for PPA improvement across the design stack
Drive fast design iterations through innovative approaches
Benefits
Opportunity to work on cutting-edge wafer products
Collaborative and innovative work environment
Exposure to advanced ASIC design methodologies
Potential for career growth in a rapidly evolving field
Access to resources for professional development
Full Job Description
What We're Looking For:
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.
Ideal Background:
An ideal candidate will have:
Hands-on experience with multiple advanced node tapeouts
Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
Understanding of PPA improvement and what levers exist for each level of the stack
Ability to think creatively about methodology for fast design iterations
Nice to Have:
Hands-on experience with ASIC design process for large die (ideally reticle max) chips
Hands-on experience with ASIC design process for AI chips
Hands-on experience with multi-die/multi-chiplet/MCM designs
