Bachelor's degree (or equivalent) with 5-7 years of experience, Master’s with 3-5 years, or PhD with 0-2 years.
Must obtain and maintain a Secret clearance.
3+ years working with targeting VHDL designs on Xilinx FPGAs.
3+ years using Cadence Virtuoso tools.
5+ years in VHDL and Verilog (or system Verilog) development.
3+ years experience with ModelSim/QuestaSim simulations.
Responsibilities
Apply technical principles, theories, and concepts to provide solutions to complex problems.
Collaborate with ASIC design engineers to create comprehensive design documents.
Develop, enhance, and debug VHDL/Verilog for chip designs.
Verify design functionality using HDL simulators like ModelSim or Xcelium.
Conduct CDC and RDC verification, and implement DFT techniques.
Port RTL to FPGA prototyping boards effectively.
Execute place and route prior to tapeout including CTS, static timing analysis, and power analysis.
Benefits
Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short and Long-Term Disability
Retirement and Savings plans
Learning and Development opportunities
Wellness programs
Full Job Description
Responsibilities
Responsibilities -
The successful candidate should be at the Career level with a complete understanding and wide application of technical principles, theories and concepts.
Working under only general direction, provides technical solutions to a wide range of difficult problems.
As such, you will be part of a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
This includes verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
You will perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
You will develop and port the RTL to an FPGA prototyping board.
You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
You will also run static timing analysis and power analysis after the CTS and place and route.
Packaging and an evaluation board for the physical chip must also be performed.
As an ASIC Design Engineer, you will develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.
Qualifications
Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of expereince.
Must be able to obtain and maintain a Secret clearance.
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's.
Minimum 3 years experience using Cadence Virtuoso.
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog).
Minimum 3 years experience using ModelSim/QuestaSim.
Equal Pay Act
This is the projected compensation range for this position. There are differentiating factors that can impact a final salary/hourly rate, including, but not limited to, Contract Wage Determination, relevant work experience, skills and competencies that align to the specified role, geographic location (For Remote Opportunities), education and certifications as well as Federal Government Contract Labor categories. In addition, Arcfield invests in its employees beyond just compensation. Arcfield 's benefits offerings include, dependent upon position, Health Insurance, Life Insurance, Paid Time Off, Holiday Pay, Short Term and Long-Term Disability, Retirement and Savings, Learning and Development opportunities, wellness programs as well as other optional benefit elections. Min: $82,437.89 Max: $198,097.02
