Opportunity OverviewTeradyne's Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineerto contribute to the development of high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).
The ideal candidate will have2+ years of relevant industry experience in analog or mixed-signal IC design, with a solid foundation in CMOS circuit design, simulation, and characterization. Experience supporting an ASIC through tape-out and silicon validation is highly desirable.
This role provides an opportunity to develop technical expertise while working alongside experienced engineers across analog design, digital design, verification, validation, test, and EDA. The engineer will also have opportunities to apply scripting, automation, and AI-enabled tools to improve design and engineering workflows.
We are looking for someone who is curious, analytical, collaborative, and motivated to continue developing their expertise in advanced semiconductor design.
Responsibilities- Design, simulate, and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
- Perform circuit-level verification and simulation across process, voltage, and temperature (PVT) corners using Cadence EDA tools.
- Support schematic, layout, physical verification, and ASIC integration activities in collaboration with other members of the design team.
- Participate in design reviews and contribute to circuit analysis, debugging, and technical problem-solving.
- Support silicon characterization, laboratory measurements, debug, validation, and production test activities.
- Analyze simulation and laboratory data to identify performance trends and design improvements.
- Develop and maintain scripts and automation tools to improve simulation, verification, characterization, and data analysis workflows.
- Explore the use of AI-assisted engineering tools and methodologies to improve design productivity and analysis.
- Collaborate with analog, digital, validation, test, product, and EDA engineers throughout the IC development lifecycle.
- Maintain clear technical documentation and communicate design results, issues, and recommendations to the broader engineering team.
All About YouWe seek individuals who share our passion for innovation and technical excellence. Our commitment to customer success drives us to continually improve how we design and deliver industry-leading solutions.
Minimum Qualifications- Master's degree in Electrical Engineering, Computer Engineering, or a related discipline, with 2+ years of relevant industry experience in analog or mixed-signal IC design, simulation, or characterization.
- Hands-on experience with CMOS analog or mixed-signal circuit design and simulation.
- Working knowledge of common analog and mixed-signal circuit architectures, which may include PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, or CML circuits.
- Understanding of CMOS device fundamentals, semiconductor processes, PDKs, and PVT effects.
- Experience with industry-standard IC design and simulation tools, preferably Cadence.
- Experience with scripting or programming languages such as Python, SKILL, or Ocean for engineering automation or data analysis.
- Strong analytical and problem-solving skills with the ability to work effectively in a collaborative engineering environment.
- Strong written and verbal communication skills.
Preferred Qualifications- Experience supporting one or more ASICs through tape-out, silicon bring-up, characterization, or production test.
- Familiarity with advanced semiconductor technologies, including FinFET processes at 16nm or below.
- Exposure to high-frequency or high-speed analog and mixed-signal design.
- Experience with laboratory characterization and test equipment.
- Familiarity with Verilog or Verilog-A.
- Exposure to AI/ML, generative AI, or large-scale data analysis applied to semiconductor design, verification, validation, or test.
- Interest in using emerging technologies and automation to improve semiconductor engineering workflows.
CompensationThe base salary range for this role is $104,100 to $166,600. This range is a good-faith estimate, and the actual base salary will correspond with the candidate's experience, skills, qualifications, and location. The range may also fluctuate depending on market demand and geographic location.
Incentive PlanThis position is eligible for discretionary bonus(es) based on financial performance.
BenefitsTeradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation and holidays, tuition assistance programs, and more.
#LI-MD1
