AI/ML ASIC Architect

Compunnel

$160K — $190K *
Aerospace & Defense
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Mechanical, Aerospace, or Computer Engineering.
  • Minimum 9 years of relevant experience; or 7 years with a Master's degree.
  • Expertise in ASIC, SoC, and I/O subsystem architecture.
  • Strong knowledge of ARM processors and AXI interconnects.
  • Experience with GPU/TPU/xPU accelerators and ML optimization.
  • Understanding of LLM architectures and cache optimization techniques.
  • Proficiency in microarchitecture principles for performance engineering.

Responsibilities

  • Design ASIC/SoC architectures including PCIe, UCIe, CXL, and DMA engines.
  • Integrate I/O subsystems with embedded processors like x86, RISC-V, and ARM.
  • Architect GPU/TPU/xPU accelerators with high-bandwidth memory hierarchies.
  • Optimize LLM training/inference using Dense, Mixture of Experts, and multi-modal architectures.
  • Implement KV cache optimization, Flash Attention, and MoE techniques.
  • Drive optimization for large-scale GPU and ML architectures.
  • Collaborate to ensure compliance with airworthiness and enterprise standards.

Benefits

  • Collaborative work environment across cross-functional teams.
  • Opportunity to work on cutting-edge AI/ML technology and high-performance solutions.
  • Engagement with compliance standards relevant to airworthiness and enterprise.
  • Exposure to advanced ASIC and SoC design responsibilities.
Full Job Description
Job Summary

The AI/ML ASIC Architect will lead the design and optimization of advanced ASIC and SoC architectures to support large-scale machine learning workloads. This role requires deep expertise in I/O subsystems, accelerators, memory hierarchies, and AI/ML model optimization. The architect will collaborate with cross-functional teams to deliver scalable, high-performance solutions that meet airworthiness, reliability, and enterprise requirements.

Key Responsibilities

  • Design ASIC/SoC architectures including PCIe, UCIe, CXL, and DMA engines.
  • Integrate I/O subsystems with embedded processors (x86, RISC-V, ARM).
  • Architect GPU/TPU/xPU accelerators with high-bandwidth memory hierarchies.
  • Optimize LLM training/inference including Dense, Mixture of Experts (MoE), and multi-modal architectures.
  • Implement KV cache optimization, Flash Attention, and MoE techniques.
  • Drive ML system optimization for large-scale GPU and ML architectures.
  • Apply microarchitecture principles to enhance performance engineering.
  • Collaborate on compliance with airworthiness and enterprise standards.


Required Qualifications

  • Bachelor's degree in Mechanical, Aerospace, or Computer Engineering (BSME, BSAE, BSCE).
  • Minimum 9 years of relevant experience; OR Master's degree with 7 years of experience.
  • Expertise in ASIC, SoC, and I/O subsystem architecture.
  • Strong knowledge of ARM processors and AXI interconnects.
  • Experience with GPU/TPU/xPU accelerators and ML system optimization.
  • Understanding of LLM architectures, KV cache optimization, and Flash Attention.
  • Proficiency in microarchitecture principles for performance engineering.
  • Preferred Qualifications
  • Experience with UCIe, CXL, NVLink, or UALink protocols.
  • Knowledge of high-speed networking (InfiniBand, RDMA, NVLink).
  • Familiarity with transformer architectures, attention mechanisms, and model parallelism.
  • Hands-on experience with CUDA programming and GPU memory hierarchies.
  • Exposure to large-scale distributed training systems.
  • Experience with NVMe storage systems, NAND flash, and firmware/ASIC design.
  • Proficiency in Matlab or Mathcad for analysis.
  • Strong communication and leadership skills.


Certifications

  • None required; certifications in ASIC design, ML systems, or GPU programming are a plus.

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