Job Details:Job Description: The Role and Impact
As a SoC Cache Design Engineer, you will play a pivotal role in developing cutting-edge Cache subsystem design for Intel's AI SoCs. You will drive the micro architecture, register transfer level (RTL) coding, subsystem integration, and simulation processes to deliver high-quality, fully verified Cache that meet power, performance, and area targets. Your work will directly contribute to Intel's groundbreaking AI hardware solutions, ensuring they meet the rigorous demands of modern applications.
Key Responsibilities
- Evaluate architectural trade-offs to align design features with performance targets, power constraints, and system limitations.
- Define and document microarchitecture specifications for complex SoC IP blocks, implement RTL in Verilog/SystemVerilog, and deliver synthesis- and timing-clean designs.
- Collaborate closely with verification teams to ensure comprehensive validation and coverage of all design aspects.
- Develop and maintain timing constraints for IP blocks, supporting physical design teams in synthesis, timing closure, and formal equivalence checks.
- Lead silicon bring-up efforts, including post-silicon validation, debug, and performance analysis.
- Mentor junior engineers and contribute to advancing best practices for design methodology and quality assurance.
Qualifications:Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience.
- Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration.
- Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures.
- Demonstrated ability to address design challenges, including clock domain crossings, power optimization, and timing closure.
- Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization.
Preferred Qualifications
- Strong knowledge of high-speed and low-power design techniques.
- Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
- Experience in SoC multicore CPU subsystem design and GPU cache development.
- Collaborative mindset and leadership skills, with a passion for innovation and solving complex technical challenges.
Join us to shape the next generation of AI hardware and make an impact on tomorrow's technological advancements.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, California, Santa Clara
Additional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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