Basic Qualifications Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.
Clearance Requirements:
Candidates must be able to obtain a U.S. Department of DefenseTS/SCI securityclearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position
Primary Job Qualifications:
We encourage you to apply if you have any of these preferred skills or experiences:
- In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
- In-depth knowledge ofSystem Verilogobject orientedprogramming and theUniversal Verification Methodology (UVM)
- UnderstandsUVM TestbenchArchitectures
- Comfortable using and developing UVMagents, bus functionalmodels
- Understands different types ofcoverage, usage of cover classes, cover points, etc
- Experience with predictive testbench components,functional coverageandassertions
- Experience withconstrained randomtesting
- Experience with theRegister Abstraction Layer
- Familiarity withrequirements-based verification, requirement tracing, and developing requirement verification strategies etc
- Experience with scripting languages such as Linusshell scripts, TCL, Python
- Familiarity with usingFormalVerification tools, code coverage, writing waivers etc
- Familiarity with the following are also helpful
- Questa Verification IP (QVIP)
- Developing UVM testbenches for designs implemented inXilinxdevices with XilinxIPandSoCs
- AXIprotocols, PCIe, Space Wire, and Ethernet interfaces
- DSPfunctions and common signal processing components
- Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
- Continuous Integration features ofGITLab
Duties and Tasks:Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developmentsDetermines architecture, system simulation and detailed design approachDefines module interfaces and all aspects of device design and simulationCreates test and simulation plans that establish functional criteriaVerifies test results and analyzes performanceMay also review vendor capabilities and simulation toolsParticipates in the improvement of the ASIC/FPGA organizational processesSupports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycleMay provide leadership and/or direction to lower level employeesIndependently determines approach to solutionsContributes to the completion of major programs and projectsPlans and executes project tasks for activities described above
General Knowledge, Skills and Abilities:This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theoriesProficient in the principles and techniques of ASIC/FPGA design and the design processKeeps abreast of technology trendsProficient awareness of business objectives and Engineerings role in achievingProficient in Microsoft Office applicationsProficient written and verbal communications skillsAbility to think creativelyAbility to multi-taskProficient skill in communicating issues, impacts, and corrective actionsRegular contact with senior levels of internal work groupsWorks under limited directionContact with project leaders and other professionals within the Engineering department and with project teams across the companySome contact with external customers
What sets you apart:
- Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and design
- Collaborative, creative thinker with high proficiency in technical problem solving
- Team player with effective communication and presentation skills
- Experience designing high speed interfaces and complex memory designs
- Commitment to ongoing professional development for yourself and others
- Identifies opportunities to apply AI for continuous improvement and innovation
Our Commitment to You:
- An exciting career path with opportunities for continuous learning and development.
- Research oriented work, alongside award winning teams developing practical solutions for our nations security
- Flexible schedules with every other Friday off work, if desired (9/80 schedule)
- Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more
- See more at gdmissionsystems.com/careers/why-work-for-us/benefits
Workplace Options:This position is fully remote, on-site or hybrid/flex, as mutually agreed.You will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale
Key Words:Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing
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Salary NoteThis estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
Combined Salary RangeUSD $122,785.00 - USD $136,215.00 /Yr.